[clang] [llvm] [LLVM] Trim intrinsics (PR #112791)
Rahul Joshi via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 18 05:11:08 PDT 2024
https://github.com/jurahul updated https://github.com/llvm/llvm-project/pull/112791
>From dcd2b7f501bd186e188f2be6242f87130d1ece66 Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Wed, 16 Oct 2024 14:00:52 -0700
Subject: [PATCH] [LLVM] Trim intrinsics
---
.../GlobalConstructorFunction.hlsl | 1 +
clang/test/CodeGenHLSL/GlobalDestructors.hlsl | 1 +
.../builtins/RWBuffer-elementtype.hlsl | 1 +
.../StructuredBuffer-elementtype.hlsl | 1 +
.../builtins/StructuredBuffer-subscript.hlsl | 1 +
clang/test/CodeGenHLSL/builtins/all.hlsl | 2 +
clang/test/CodeGenHLSL/builtins/any.hlsl | 2 +
.../CodeGenHLSL/builtins/clamp-builtin.hlsl | 1 +
clang/test/CodeGenHLSL/builtins/clamp.hlsl | 1 +
clang/test/CodeGenHLSL/builtins/cross.hlsl | 2 +
clang/test/CodeGenHLSL/builtins/degrees.hlsl | 2 +
clang/test/CodeGenHLSL/builtins/dot.hlsl | 2 +
clang/test/CodeGenHLSL/builtins/frac.hlsl | 2 +
clang/test/CodeGenHLSL/builtins/isinf.hlsl | 1 +
clang/test/CodeGenHLSL/builtins/length.hlsl | 1 +
clang/test/CodeGenHLSL/builtins/lerp.hlsl | 2 +
clang/test/CodeGenHLSL/builtins/mad.hlsl | 2 +
.../test/CodeGenHLSL/builtins/normalize.hlsl | 1 +
clang/test/CodeGenHLSL/builtins/radians.hlsl | 2 +
clang/test/CodeGenHLSL/builtins/rsqrt.hlsl | 2 +
clang/test/CodeGenHLSL/builtins/saturate.hlsl | 2 +
clang/test/CodeGenHLSL/builtins/sign.hlsl | 2 +
clang/test/CodeGenHLSL/builtins/step.hlsl | 2 +
.../builtins/wave_get_lane_index_simple.hlsl | 2 +
.../builtins/wave_is_first_lane.hlsl | 2 +
.../implicit-norecurse-attrib.hlsl | 1 +
.../test/CodeGenHLSL/inline-constructors.hlsl | 1 +
clang/test/CodeGenHLSL/inline-functions.hlsl | 1 +
.../semantics/DispatchThreadID.hlsl | 2 +
.../semantics/GroupIndex-codegen.hlsl | 1 +
clang/test/SemaHLSL/GlobalConstructors.hlsl | 1 +
llvm/CMakeLists.txt | 35 ++++++
llvm/include/llvm/IR/CMakeLists.txt | 40 +++----
llvm/lib/IR/Intrinsics.cpp | 9 +-
llvm/lib/Target/AArch64/CMakeLists.txt | 8 +-
llvm/lib/Target/AMDGPU/CMakeLists.txt | 14 +--
llvm/lib/Target/ARC/CMakeLists.txt | 4 +-
llvm/lib/Target/ARM/CMakeLists.txt | 8 +-
llvm/lib/Target/AVR/CMakeLists.txt | 4 +-
llvm/lib/Target/BPF/CMakeLists.txt | 6 +-
llvm/lib/Target/CSKY/CMakeLists.txt | 4 +-
llvm/lib/Target/DirectX/CMakeLists.txt | 3 +-
llvm/lib/Target/Hexagon/CMakeLists.txt | 4 +-
llvm/lib/Target/Lanai/CMakeLists.txt | 4 +-
llvm/lib/Target/LoongArch/CMakeLists.txt | 4 +-
llvm/lib/Target/M68k/CMakeLists.txt | 6 +-
llvm/lib/Target/MSP430/CMakeLists.txt | 4 +-
llvm/lib/Target/Mips/CMakeLists.txt | 8 +-
llvm/lib/Target/NVPTX/CMakeLists.txt | 4 +-
llvm/lib/Target/PowerPC/CMakeLists.txt | 8 +-
llvm/lib/Target/RISCV/CMakeLists.txt | 6 +-
llvm/lib/Target/SPIRV/CMakeLists.txt | 4 +-
llvm/lib/Target/Sparc/CMakeLists.txt | 4 +-
llvm/lib/Target/SystemZ/CMakeLists.txt | 4 +-
llvm/lib/Target/VE/CMakeLists.txt | 4 +-
llvm/lib/Target/WebAssembly/CMakeLists.txt | 6 +-
llvm/lib/Target/X86/CMakeLists.txt | 9 +-
llvm/lib/Target/XCore/CMakeLists.txt | 4 +-
llvm/lib/Target/Xtensa/CMakeLists.txt | 4 +-
.../Analysis/CtxProfAnalysis/full-cycle.ll | 1 +
.../DXILResource/buffer-frombinding.ll | 1 +
llvm/test/Analysis/MemorySSA/pr36883.ll | 1 +
.../Analysis/ValueTracking/aarch64.irg.ll | 1 +
.../ValueTracking/knownbits-x86-hadd-hsub.ll | 1 +
.../amdgpu-image-atomic-attributes.ll | 1 +
.../Assembler/autoupgrade-wasm-intrinsics.ll | 1 +
.../opaque-ptr-intrinsic-remangling.ll | 1 +
llvm/test/Bitcode/aarch64-addp-upgrade.ll | 1 +
llvm/test/Bitcode/aarch64-bf16-upgrade.ll | 1 +
llvm/test/Bitcode/arm-bf16-upgrade.ll | 1 +
llvm/test/Bitcode/arm-intrinsics.ll | 1 +
.../intrinsics-struct-upgrade-attributes.ll | 1 +
.../test/Bitcode/intrinsics-struct-upgrade.ll | 1 +
llvm/test/Bitcode/ptest-new.ll | 1 +
llvm/test/Bitcode/upgrade-aarch64-ldstxr.ll | 1 +
.../Bitcode/upgrade-aarch64-sve-intrinsics.ll | 1 +
llvm/test/CodeGen/AArch64/arm64-vshift.ll | 1 +
.../MemorySanitizer/AArch64/arm64-vshift.ll | 1 +
.../MemorySanitizer/AArch64/neon_vst.ll | 1 +
.../MemorySanitizer/AArch64/neon_vst_float.ll | 1 +
.../MemorySanitizer/AArch64/neon_vst_lane.ll | 1 +
.../AArch64/neon_vst_origins.ll | 1 +
llvm/test/TableGen/ContextlessPredicates.td | 4 +-
llvm/test/TableGen/DAGDefaultOps.td | 2 +-
llvm/test/TableGen/DefaultOpsGlobalISel.td | 2 +-
llvm/test/TableGen/DuplicateFieldValues.td | 2 +-
llvm/test/TableGen/FastISelEmitter.td | 2 +-
.../TableGen/GlobalISelEmitter-PR39045.td | 2 +-
.../GlobalISelEmitter-SDNodeXForm-timm.td | 2 +-
.../GlobalISelEmitter-atomic_store.td | 2 +-
.../TableGen/GlobalISelEmitter-frameindex.td | 2 +-
.../GlobalISelEmitter-immAllZeroOne.td | 4 +-
...lobalISelEmitter-immarg-literal-pattern.td | 2 +-
.../GlobalISelEmitter-input-discard.td | 2 +-
...obalISelEmitter-multiple-output-discard.td | 2 +-
.../GlobalISelEmitter-multiple-output.td | 2 +-
.../GlobalISelEmitter-nested-subregs.td | 2 +-
...GlobalISelEmitter-notype-output-pattern.td | 2 +-
.../GlobalISelEmitter-output-discard.td | 2 +-
llvm/test/TableGen/GlobalISelEmitter-setcc.td | 2 +-
.../TableGen/GlobalISelEmitter-zero-instr.td | 2 +-
.../TableGen/GlobalISelEmitter-zero-reg.td | 2 +-
llvm/test/TableGen/GlobalISelEmitter.td | 6 +-
.../GlobalISelEmitterCustomPredicate.td | 2 +-
llvm/test/TableGen/GlobalISelEmitterFlags.td | 2 +-
.../test/TableGen/GlobalISelEmitterHwModes.td | 2 +-
.../GlobalISelEmitterMatchTableOptimizer.td | 2 +-
...rMatchTableOptimizerSameOperand-invalid.td | 2 +-
...elEmitterMatchTableOptimizerSameOperand.td | 2 +-
.../GlobalISelEmitterOverloadedPtr.td | 2 +-
.../TableGen/GlobalISelEmitterRegSequence.td | 2 +-
.../GlobalISelEmitterSkippedPatterns.td | 4 +-
llvm/test/TableGen/GlobalISelEmitterSubreg.td | 2 +-
.../TableGen/GlobalISelEmitterVariadic.td | 2 +-
llvm/test/TableGen/HasNoUse.td | 4 +-
llvm/test/TableGen/RelTest.td | 2 +-
llvm/test/TableGen/address-space-patfrags.td | 4 +-
llvm/test/TableGen/dag-isel-complexpattern.td | 2 +-
.../TableGen/dag-isel-regclass-emit-enum.td | 2 +-
llvm/test/TableGen/dag-isel-res-order.td | 2 +-
llvm/test/TableGen/dag-isel-subregs.td | 2 +-
llvm/test/TableGen/def-multiple-operands.td | 2 +-
.../TableGen/get-operand-type-no-expand.td | 4 +-
llvm/test/TableGen/get-operand-type.td | 2 +-
llvm/test/TableGen/gisel-physreg-input.td | 2 +-
llvm/test/TableGen/immarg-predicated.td | 2 +-
llvm/test/TableGen/immarg.td | 2 +-
llvm/test/TableGen/intrinsic-attrs.td | 2 +-
.../test/TableGen/intrinsic-duplicate-name.td | 2 +-
llvm/test/TableGen/intrinsic-long-name.td | 2 +-
.../TableGen/intrinsic-overload-conflict.td | 4 +-
llvm/test/TableGen/intrinsic-prefix-error.td | 2 +-
llvm/test/TableGen/intrinsic-struct.td | 6 +-
...ic-target-prefix-for-target-independent.td | 2 +-
llvm/test/TableGen/intrinsic-varargs.td | 2 +-
.../TableGen/invalid-type-cast-patfrags.td | 8 +-
.../TableGen/multiple-type-casts-patfrags.td | 4 +-
llvm/test/TableGen/predicate-patfags.td | 8 +-
llvm/test/TableGen/simplify-patfrag.td | 4 +-
.../TableGen/Basic/CodeGenIntrinsics.cpp | 88 ++++++++++++---
llvm/utils/TableGen/Basic/CodeGenIntrinsics.h | 19 +++-
.../TableGen/Common/CodeGenDAGPatterns.h | 17 +--
llvm/utils/TableGen/IntrinsicEmitter.cpp | 103 +++++++++++-------
143 files changed, 436 insertions(+), 235 deletions(-)
diff --git a/clang/test/CodeGenHLSL/GlobalConstructorFunction.hlsl b/clang/test/CodeGenHLSL/GlobalConstructorFunction.hlsl
index c0eb1b138ed047..dd1d31d15ff675 100644
--- a/clang/test/CodeGenHLSL/GlobalConstructorFunction.hlsl
+++ b/clang/test/CodeGenHLSL/GlobalConstructorFunction.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -emit-llvm -disable-llvm-passes %s -o - | FileCheck %s --check-prefixes=CHECK,NOINLINE
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -emit-llvm -O0 %s -o - | FileCheck %s --check-prefixes=CHECK,INLINE
diff --git a/clang/test/CodeGenHLSL/GlobalDestructors.hlsl b/clang/test/CodeGenHLSL/GlobalDestructors.hlsl
index f98318601134bb..4227f85033c778 100644
--- a/clang/test/CodeGenHLSL/GlobalDestructors.hlsl
+++ b/clang/test/CodeGenHLSL/GlobalDestructors.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -emit-llvm -disable-llvm-passes %s -o - | FileCheck %s --check-prefixes=CS,NOINLINE,CHECK
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -emit-llvm -disable-llvm-passes %s -o - | FileCheck %s --check-prefixes=LIB,NOINLINE,CHECK
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -emit-llvm -O0 %s -o - | FileCheck %s --check-prefixes=INLINE,CHECK
diff --git a/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl b/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl
index fa81b53fd9bddc..66a2e15889d11d 100644
--- a/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.2-compute -finclude-default-header -fnative-half-type -emit-llvm -o - %s | FileCheck %s
// NOTE: The type name number and whether the struct is packed or not will mostly
diff --git a/clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl b/clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl
index 435a904327a26a..a5b225df49f1db 100644
--- a/clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.2-compute -finclude-default-header -fnative-half-type -emit-llvm -o - %s | FileCheck %s
// NOTE: The number in type name and whether the struct is packed or not will mostly
diff --git a/clang/test/CodeGenHLSL/builtins/StructuredBuffer-subscript.hlsl b/clang/test/CodeGenHLSL/builtins/StructuredBuffer-subscript.hlsl
index 89bde9236288fc..e11919fa88338e 100644
--- a/clang/test/CodeGenHLSL/builtins/StructuredBuffer-subscript.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/StructuredBuffer-subscript.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -emit-llvm -o - -O0 %s | FileCheck %s
StructuredBuffer<int> In;
diff --git a/clang/test/CodeGenHLSL/builtins/all.hlsl b/clang/test/CodeGenHLSL/builtins/all.hlsl
index 39f364c5953d60..ec315b7b26c9c5 100644
--- a/clang/test/CodeGenHLSL/builtins/all.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/all.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: spirv-unknown-vulkan-compute %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/any.hlsl b/clang/test/CodeGenHLSL/builtins/any.hlsl
index 3d9d8e9e689ed0..4ceca3b78e2503 100644
--- a/clang/test/CodeGenHLSL/builtins/any.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/any.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: spirv-unknown-vulkan-compute %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl b/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
index e3ef26429e7e40..b6721b3fa8e2f2 100644
--- a/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple dxil-pc-shadermodel6.3-library %s -fnative-half-type -emit-llvm -disable-llvm-passes -o - | FileCheck %s
// CHECK-LABEL: builtin_test_clamp_int4
diff --git a/clang/test/CodeGenHLSL/builtins/clamp.hlsl b/clang/test/CodeGenHLSL/builtins/clamp.hlsl
index af8f6b9733a071..97f68c0f1bdfa4 100644
--- a/clang/test/CodeGenHLSL/builtins/clamp.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/clamp.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.3-library %s \
// RUN: -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \
// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF
diff --git a/clang/test/CodeGenHLSL/builtins/cross.hlsl b/clang/test/CodeGenHLSL/builtins/cross.hlsl
index eba710c905bf46..78b5f456450e87 100644
--- a/clang/test/CodeGenHLSL/builtins/cross.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/cross.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/degrees.hlsl b/clang/test/CodeGenHLSL/builtins/degrees.hlsl
index 9e131f4badc19a..304c0b5e43916c 100644
--- a/clang/test/CodeGenHLSL/builtins/degrees.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/degrees.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/dot.hlsl b/clang/test/CodeGenHLSL/builtins/dot.hlsl
index 3f6be04a595e23..bcbd181c948b1f 100644
--- a/clang/test/CodeGenHLSL/builtins/dot.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/dot.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/frac.hlsl b/clang/test/CodeGenHLSL/builtins/frac.hlsl
index f0fbba978c0237..76b7c3a6c9a3c0 100644
--- a/clang/test/CodeGenHLSL/builtins/frac.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/frac.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/isinf.hlsl b/clang/test/CodeGenHLSL/builtins/isinf.hlsl
index df44fc4a91dfd0..ed85d9a3f9c8d9 100644
--- a/clang/test/CodeGenHLSL/builtins/isinf.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/isinf.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/length.hlsl b/clang/test/CodeGenHLSL/builtins/length.hlsl
index 9b0293c218a5de..cd2b58197f6653 100644
--- a/clang/test/CodeGenHLSL/builtins/length.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/length.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/lerp.hlsl b/clang/test/CodeGenHLSL/builtins/lerp.hlsl
index b11046894bd889..66425ee30cbf86 100644
--- a/clang/test/CodeGenHLSL/builtins/lerp.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/lerp.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/mad.hlsl b/clang/test/CodeGenHLSL/builtins/mad.hlsl
index 265a2552c80fb4..8dea8763169b87 100644
--- a/clang/test/CodeGenHLSL/builtins/mad.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/mad.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/normalize.hlsl b/clang/test/CodeGenHLSL/builtins/normalize.hlsl
index d14e7c70ce0653..bb56663bbf31d9 100644
--- a/clang/test/CodeGenHLSL/builtins/normalize.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/normalize.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/radians.hlsl b/clang/test/CodeGenHLSL/builtins/radians.hlsl
index 774300525dbf02..283130888fe850 100644
--- a/clang/test/CodeGenHLSL/builtins/radians.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/radians.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/rsqrt.hlsl b/clang/test/CodeGenHLSL/builtins/rsqrt.hlsl
index b1b53fc187da67..fb05d285917d54 100644
--- a/clang/test/CodeGenHLSL/builtins/rsqrt.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/rsqrt.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/saturate.hlsl b/clang/test/CodeGenHLSL/builtins/saturate.hlsl
index c221f6e0f2c36f..b0a3b34db75720 100644
--- a/clang/test/CodeGenHLSL/builtins/saturate.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/saturate.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.3-library %s \
// RUN: -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \
// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF -Dtar=dx
diff --git a/clang/test/CodeGenHLSL/builtins/sign.hlsl b/clang/test/CodeGenHLSL/builtins/sign.hlsl
index 1cdefa815b103f..bc7e7d4c30e5cf 100644
--- a/clang/test/CodeGenHLSL/builtins/sign.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/sign.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/step.hlsl b/clang/test/CodeGenHLSL/builtins/step.hlsl
index 8ef52794a3be5d..ef0f15712fdf0b 100644
--- a/clang/test/CodeGenHLSL/builtins/step.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/step.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
diff --git a/clang/test/CodeGenHLSL/builtins/wave_get_lane_index_simple.hlsl b/clang/test/CodeGenHLSL/builtins/wave_get_lane_index_simple.hlsl
index 8e1f2d69e74329..05f1fe1aa8923d 100644
--- a/clang/test/CodeGenHLSL/builtins/wave_get_lane_index_simple.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/wave_get_lane_index_simple.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
// RUN: spirv-pc-vulkan-library %s -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
// RUN: --check-prefixes=CHECK,CHECK-SPIRV
diff --git a/clang/test/CodeGenHLSL/builtins/wave_is_first_lane.hlsl b/clang/test/CodeGenHLSL/builtins/wave_is_first_lane.hlsl
index 2fb6defb896f90..5317c906480a63 100644
--- a/clang/test/CodeGenHLSL/builtins/wave_is_first_lane.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/wave_is_first_lane.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
// RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \
// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV
diff --git a/clang/test/CodeGenHLSL/implicit-norecurse-attrib.hlsl b/clang/test/CodeGenHLSL/implicit-norecurse-attrib.hlsl
index 5efecc1489afca..b097959a3c4ed5 100644
--- a/clang/test/CodeGenHLSL/implicit-norecurse-attrib.hlsl
+++ b/clang/test/CodeGenHLSL/implicit-norecurse-attrib.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -x hlsl -triple dxil-pc-shadermodel6.3-library -finclude-default-header %s -emit-llvm -disable-llvm-passes -o - | FileCheck %s
// RUN: %clang_cc1 -x hlsl -triple dxil-pc-shadermodel6.0-compute -finclude-default-header %s -emit-llvm -disable-llvm-passes -o - | FileCheck %s
diff --git a/clang/test/CodeGenHLSL/inline-constructors.hlsl b/clang/test/CodeGenHLSL/inline-constructors.hlsl
index b0d5a783fb3725..1baa34eea4afff 100644
--- a/clang/test/CodeGenHLSL/inline-constructors.hlsl
+++ b/clang/test/CodeGenHLSL/inline-constructors.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -std=hlsl202x -emit-llvm -o - -disable-llvm-passes %s | FileCheck %s --check-prefixes=CHECK,NOINLINE
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -std=hlsl202x -emit-llvm -o - -disable-llvm-passes %s | FileCheck %s --check-prefixes=CHECK,NOINLINE
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -std=hlsl202x -emit-llvm -o - -O0 %s | FileCheck %s --check-prefixes=CHECK,INLINE
diff --git a/clang/test/CodeGenHLSL/inline-functions.hlsl b/clang/test/CodeGenHLSL/inline-functions.hlsl
index fa9c88db26dfc2..001df0dcac0e5e 100644
--- a/clang/test/CodeGenHLSL/inline-functions.hlsl
+++ b/clang/test/CodeGenHLSL/inline-functions.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library %s -emit-llvm -disable-llvm-passes -o - | FileCheck %s --check-prefixes=CHECK,NOINLINE
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library %s -emit-llvm -O0 -o - | FileCheck %s --check-prefixes=CHECK,INLINE
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library %s -emit-llvm -O1 -o - | FileCheck %s --check-prefixes=CHECK,INLINE
diff --git a/clang/test/CodeGenHLSL/semantics/DispatchThreadID.hlsl b/clang/test/CodeGenHLSL/semantics/DispatchThreadID.hlsl
index 975a7264fd3f01..ce45c63a419ce9 100644
--- a/clang/test/CodeGenHLSL/semantics/DispatchThreadID.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/DispatchThreadID.hlsl
@@ -1,3 +1,5 @@
+// REQUIRES: directx-registered-target
+// REQUIRES: spirv-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -emit-llvm -finclude-default-header -disable-llvm-passes -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-DXIL -DTARGET=dx
// RUN: %clang_cc1 -triple spirv-linux-vulkan-library -x hlsl -emit-llvm -finclude-default-header -disable-llvm-passes -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV -DTARGET=spv
diff --git a/clang/test/CodeGenHLSL/semantics/GroupIndex-codegen.hlsl b/clang/test/CodeGenHLSL/semantics/GroupIndex-codegen.hlsl
index ea358c411997d0..1604976d4ae179 100644
--- a/clang/test/CodeGenHLSL/semantics/GroupIndex-codegen.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/GroupIndex-codegen.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -x hlsl -emit-llvm -disable-llvm-passes -o - -hlsl-entry main %s | FileCheck %s
[numthreads(1,1,1)]
diff --git a/clang/test/SemaHLSL/GlobalConstructors.hlsl b/clang/test/SemaHLSL/GlobalConstructors.hlsl
index ddd09422d74852..dc12053b178316 100644
--- a/clang/test/SemaHLSL/GlobalConstructors.hlsl
+++ b/clang/test/SemaHLSL/GlobalConstructors.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -fsyntax-only %s -verify
int i;
diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index cde4a999ea2e74..1c153ce83c8c38 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -625,6 +625,41 @@ set(LLVM_TARGETS_TO_BUILD
${LLVM_EXPERIMENTAL_TARGETS_TO_BUILD})
list(REMOVE_DUPLICATES LLVM_TARGETS_TO_BUILD)
+#set(ENABLED_INTRINSIC_TARGETS ${LLVM_ALL_TARGETS} ${LLVM_ALL_EXPERIMENTAL_TARGETS})
+set(ENABLED_INTRINSIC_TARGETS ${LLVM_TARGETS_TO_BUILD})
+
+# Build a list of intrinsic target prefixes for targets that have been enabled.
+string(REPLACE ";" "," ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(CONCAT ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}" ",")
+string(REPLACE "AMDGPU" "R600,AMDGCN" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "PowerPC" "ppc" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "SPIRV" "spv" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "NVPTX" "nvvm" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "DirectX" "dx" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "WebAssembly" "wasm" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "SystemZ" "s390" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+# Remove target prefixes that do not have any intrinscs defined for them.
+string(REPLACE "M68k," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "ARC," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "AVR," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "CSKY," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "Lanai," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "Sparc," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "MSP430," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "Xtensa," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+
+# strip the last ,
+string(LENGTH "${ENABLED_INTRINSIC_TARGETS}" enabled_len)
+math(EXPR enabled_len "${enabled_len} - 1")
+string(SUBSTRING "${ENABLED_INTRINSIC_TARGETS}" 0 "${enabled_len}" ENABLED_INTRINSIC_TARGETS)
+if ("${ENABLED_INTRINSIC_TARGETS}" STREQUAL "")
+ set(ENABLED_INTRINSIC_TARGETS "none")
+else()
+ string(TOLOWER ${ENABLED_INTRINSIC_TARGETS} ENABLED_INTRINSIC_TARGETS)
+endif()
+message(STATUS "Enabling intrinsic targets: ${ENABLED_INTRINSIC_TARGETS}")
+set(ENABLED_INTRINSIC_TARGETS --enabled-targets=${ENABLED_INTRINSIC_TARGETS})
+
if (NOT CMAKE_SYSTEM_NAME MATCHES "OS390")
option(LLVM_ENABLE_PIC "Build Position-Independent Code" ON)
endif()
diff --git a/llvm/include/llvm/IR/CMakeLists.txt b/llvm/include/llvm/IR/CMakeLists.txt
index 468d663796ed43..719d64fc292539 100644
--- a/llvm/include/llvm/IR/CMakeLists.txt
+++ b/llvm/include/llvm/IR/CMakeLists.txt
@@ -2,24 +2,24 @@ set(LLVM_TARGET_DEFINITIONS Attributes.td)
tablegen(LLVM Attributes.inc -gen-attrs)
set(LLVM_TARGET_DEFINITIONS Intrinsics.td)
-tablegen(LLVM IntrinsicImpl.inc -gen-intrinsic-impl)
-tablegen(LLVM IntrinsicEnums.inc -gen-intrinsic-enums)
-tablegen(LLVM IntrinsicsAArch64.h -gen-intrinsic-enums -intrinsic-prefix=aarch64)
-tablegen(LLVM IntrinsicsAMDGPU.h -gen-intrinsic-enums -intrinsic-prefix=amdgcn)
-tablegen(LLVM IntrinsicsARM.h -gen-intrinsic-enums -intrinsic-prefix=arm)
-tablegen(LLVM IntrinsicsBPF.h -gen-intrinsic-enums -intrinsic-prefix=bpf)
-tablegen(LLVM IntrinsicsDirectX.h -gen-intrinsic-enums -intrinsic-prefix=dx)
-tablegen(LLVM IntrinsicsHexagon.h -gen-intrinsic-enums -intrinsic-prefix=hexagon)
-tablegen(LLVM IntrinsicsLoongArch.h -gen-intrinsic-enums -intrinsic-prefix=loongarch)
-tablegen(LLVM IntrinsicsMips.h -gen-intrinsic-enums -intrinsic-prefix=mips)
-tablegen(LLVM IntrinsicsNVPTX.h -gen-intrinsic-enums -intrinsic-prefix=nvvm)
-tablegen(LLVM IntrinsicsPowerPC.h -gen-intrinsic-enums -intrinsic-prefix=ppc)
-tablegen(LLVM IntrinsicsR600.h -gen-intrinsic-enums -intrinsic-prefix=r600)
-tablegen(LLVM IntrinsicsRISCV.h -gen-intrinsic-enums -intrinsic-prefix=riscv)
-tablegen(LLVM IntrinsicsSPIRV.h -gen-intrinsic-enums -intrinsic-prefix=spv)
-tablegen(LLVM IntrinsicsS390.h -gen-intrinsic-enums -intrinsic-prefix=s390)
-tablegen(LLVM IntrinsicsWebAssembly.h -gen-intrinsic-enums -intrinsic-prefix=wasm)
-tablegen(LLVM IntrinsicsX86.h -gen-intrinsic-enums -intrinsic-prefix=x86)
-tablegen(LLVM IntrinsicsXCore.h -gen-intrinsic-enums -intrinsic-prefix=xcore)
-tablegen(LLVM IntrinsicsVE.h -gen-intrinsic-enums -intrinsic-prefix=ve)
+tablegen(LLVM IntrinsicImpl.inc -gen-intrinsic-impl ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicEnums.inc -gen-intrinsic-enums ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsAArch64.h -gen-intrinsic-enums -intrinsic-prefix=aarch64 ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsAMDGPU.h -gen-intrinsic-enums -intrinsic-prefix=amdgcn ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsARM.h -gen-intrinsic-enums -intrinsic-prefix=arm ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsBPF.h -gen-intrinsic-enums -intrinsic-prefix=bpf ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsDirectX.h -gen-intrinsic-enums -intrinsic-prefix=dx ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsHexagon.h -gen-intrinsic-enums -intrinsic-prefix=hexagon ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsLoongArch.h -gen-intrinsic-enums -intrinsic-prefix=loongarch ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsMips.h -gen-intrinsic-enums -intrinsic-prefix=mips ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsNVPTX.h -gen-intrinsic-enums -intrinsic-prefix=nvvm ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsPowerPC.h -gen-intrinsic-enums -intrinsic-prefix=ppc ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsR600.h -gen-intrinsic-enums -intrinsic-prefix=r600 ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsRISCV.h -gen-intrinsic-enums -intrinsic-prefix=riscv ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsSPIRV.h -gen-intrinsic-enums -intrinsic-prefix=spv ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsS390.h -gen-intrinsic-enums -intrinsic-prefix=s390 ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsWebAssembly.h -gen-intrinsic-enums -intrinsic-prefix=wasm ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsX86.h -gen-intrinsic-enums -intrinsic-prefix=x86 ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsXCore.h -gen-intrinsic-enums -intrinsic-prefix=xcore ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsVE.h -gen-intrinsic-enums -intrinsic-prefix=ve ${ENABLED_INTRINSIC_TARGETS})
add_public_tablegen_target(intrinsics_gen)
diff --git a/llvm/lib/IR/Intrinsics.cpp b/llvm/lib/IR/Intrinsics.cpp
index 1b92daf15b463e..70472c78c8af9a 100644
--- a/llvm/lib/IR/Intrinsics.cpp
+++ b/llvm/lib/IR/Intrinsics.cpp
@@ -45,12 +45,12 @@ static constexpr const char *const IntrinsicNameTable[] = {
};
StringRef Intrinsic::getBaseName(ID id) {
- assert(id < num_intrinsics && "Invalid intrinsic ID!");
+ assert(id < Intrinsic::num_active_intrinsics && "Invalid intrinsic ID!");
return IntrinsicNameTable[id];
}
StringRef Intrinsic::getName(ID id) {
- assert(id < num_intrinsics && "Invalid intrinsic ID!");
+ assert(id < Intrinsic::num_active_intrinsics && "Invalid intrinsic ID!");
assert(!Intrinsic::isOverloaded(id) &&
"This version of getName does not support overloading");
return getBaseName(id);
@@ -157,8 +157,7 @@ static std::string getMangledTypeStr(Type *Ty, bool &HasUnnamedType) {
static std::string getIntrinsicNameImpl(Intrinsic::ID Id, ArrayRef<Type *> Tys,
Module *M, FunctionType *FT,
bool EarlyModuleCheck) {
-
- assert(Id < Intrinsic::num_intrinsics && "Invalid intrinsic ID!");
+ assert(Id < Intrinsic::num_active_intrinsics && "Invalid intrinsic ID!");
assert((Tys.empty() || Intrinsic::isOverloaded(Id)) &&
"This version of getName is for overloaded intrinsics only");
(void)EarlyModuleCheck;
@@ -453,6 +452,7 @@ void Intrinsic::getIntrinsicInfoTableEntries(
ID id, SmallVectorImpl<IITDescriptor> &T) {
static_assert(sizeof(IIT_Table[0]) == 2,
"Expect 16-bit entries in IIT_Table");
+ assert(id < Intrinsic::num_active_intrinsics);
// Check to see if the intrinsic's type was expressible by the table.
uint16_t TableVal = IIT_Table[id - 1];
@@ -610,6 +610,7 @@ FunctionType *Intrinsic::getType(LLVMContext &Context, ID id,
}
bool Intrinsic::isOverloaded(ID id) {
+ assert(id < Intrinsic::num_active_intrinsics);
#define GET_INTRINSIC_OVERLOAD_TABLE
#include "llvm/IR/IntrinsicImpl.inc"
#undef GET_INTRINSIC_OVERLOAD_TABLE
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt
index da13db8e68b0e6..deca0ab4f839e1 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -6,10 +6,10 @@ tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
-tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="AArch64O0PreLegalizerCombiner")
tablegen(LLVM AArch64GenPreLegalizeGICombiner.inc -gen-global-isel-combiner
@@ -18,7 +18,7 @@ tablegen(LLVM AArch64GenPostLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="AArch64PostLegalizerCombiner")
tablegen(LLVM AArch64GenPostLegalizeGILowering.inc -gen-global-isel-combiner
-combiners="AArch64PostLegalizerLowering")
-tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt
index fed29c3e14aae2..e50a56231160ac 100644
--- a/llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -2,12 +2,12 @@ add_llvm_component_group(AMDGPU)
set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
-tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
+tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
@@ -16,20 +16,20 @@ tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)
tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
-tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AMDGPUGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="AMDGPUPreLegalizerCombiner")
tablegen(LLVM AMDGPUGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
- -combiners="AMDGPUPostLegalizerCombiner")
+ -combiners="AMDGPUPostLegalizerCombiner" ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AMDGPUGenRegBankGICombiner.inc -gen-global-isel-combiner
-combiners="AMDGPURegBankCombiner")
set(LLVM_TARGET_DEFINITIONS R600.td)
tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM R600GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM R600GenDFAPacketizer.inc -gen-dfa-packetizer)
-tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM R600GenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM R600GenRegisterInfo.inc -gen-register-info)
tablegen(LLVM R600GenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/ARC/CMakeLists.txt b/llvm/lib/Target/ARC/CMakeLists.txt
index 9f3c1787c5635e..0ef7f1a7174bb4 100644
--- a/llvm/lib/Target/ARC/CMakeLists.txt
+++ b/llvm/lib/Target/ARC/CMakeLists.txt
@@ -4,9 +4,9 @@ set(LLVM_TARGET_DEFINITIONS ARC.td)
tablegen(LLVM ARCGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM ARCGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM ARCGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM ARCGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM ARCGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM ARCGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM ARCGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM ARCGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM ARCGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/ARM/CMakeLists.txt b/llvm/lib/Target/ARM/CMakeLists.txt
index 3d6af28b437538..a3b5517c06fe36 100644
--- a/llvm/lib/Target/ARM/CMakeLists.txt
+++ b/llvm/lib/Target/ARM/CMakeLists.txt
@@ -5,11 +5,11 @@ set(LLVM_TARGET_DEFINITIONS ARM.td)
tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
-tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt b/llvm/lib/Target/AVR/CMakeLists.txt
index 817ba739d8418a..4fede075558e89 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS AVR.td)
tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM AVRGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/BPF/CMakeLists.txt b/llvm/lib/Target/BPF/CMakeLists.txt
index eade4cacb7100e..a876dca443c0b2 100644
--- a/llvm/lib/Target/BPF/CMakeLists.txt
+++ b/llvm/lib/Target/BPF/CMakeLists.txt
@@ -5,13 +5,13 @@ set(LLVM_TARGET_DEFINITIONS BPF.td)
tablegen(LLVM BPFGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM BPFGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM BPFGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM BPFGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM BPFGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM BPFGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM BPFGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM BPFGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM BPFGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM BPFGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM BPFGenSubtargetInfo.inc -gen-subtarget)
-tablegen(LLVM BPFGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM BPFGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM BPFGenRegisterBank.inc -gen-register-bank)
add_public_tablegen_target(BPFCommonTableGen)
diff --git a/llvm/lib/Target/CSKY/CMakeLists.txt b/llvm/lib/Target/CSKY/CMakeLists.txt
index cdce80591a2fd2..81d720d4404f03 100644
--- a/llvm/lib/Target/CSKY/CMakeLists.txt
+++ b/llvm/lib/Target/CSKY/CMakeLists.txt
@@ -6,9 +6,9 @@ tablegen(LLVM CSKYGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM CSKYGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM CSKYGenCallingConv.inc -gen-callingconv)
tablegen(LLVM CSKYGenCompressInstEmitter.inc -gen-compress-inst-emitter)
-tablegen(LLVM CSKYGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM CSKYGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM CSKYGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM CSKYGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM CSKYGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM CSKYGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/DirectX/CMakeLists.txt b/llvm/lib/Target/DirectX/CMakeLists.txt
index c8ef0ef6f7e702..328657079f685f 100644
--- a/llvm/lib/Target/DirectX/CMakeLists.txt
+++ b/llvm/lib/Target/DirectX/CMakeLists.txt
@@ -3,7 +3,7 @@ add_llvm_component_group(DirectX)
set(LLVM_TARGET_DEFINITIONS DirectX.td)
tablegen(LLVM DirectXGenSubtargetInfo.inc -gen-subtarget)
-tablegen(LLVM DirectXGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM DirectXGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM DirectXGenRegisterInfo.inc -gen-register-info)
set(LLVM_TARGET_DEFINITIONS DXIL.td)
@@ -45,6 +45,7 @@ add_llvm_target(DirectXCodeGen
FrontendHLSL
MC
SelectionDAG
+ Scalar
Support
Target
TargetParser
diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt b/llvm/lib/Target/Hexagon/CMakeLists.txt
index e8ec93dd5ee63c..2e0299c0baad45 100644
--- a/llvm/lib/Target/Hexagon/CMakeLists.txt
+++ b/llvm/lib/Target/Hexagon/CMakeLists.txt
@@ -5,10 +5,10 @@ set(LLVM_TARGET_DEFINITIONS Hexagon.td)
tablegen(LLVM HexagonGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM HexagonGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/Lanai/CMakeLists.txt b/llvm/lib/Target/Lanai/CMakeLists.txt
index 16d5f727043fe9..aff46035b6b3cf 100644
--- a/llvm/lib/Target/Lanai/CMakeLists.txt
+++ b/llvm/lib/Target/Lanai/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS Lanai.td)
tablegen(LLVM LanaiGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM LanaiGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM LanaiGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM LanaiGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM LanaiGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM LanaiGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM LanaiGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM LanaiGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM LanaiGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM LanaiGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM LanaiGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/LoongArch/CMakeLists.txt b/llvm/lib/Target/LoongArch/CMakeLists.txt
index 0f674b1b0fa9e2..fde92b1193f493 100644
--- a/llvm/lib/Target/LoongArch/CMakeLists.txt
+++ b/llvm/lib/Target/LoongArch/CMakeLists.txt
@@ -4,9 +4,9 @@ set(LLVM_TARGET_DEFINITIONS LoongArch.td)
tablegen(LLVM LoongArchGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM LoongArchGenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM LoongArchGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM LoongArchGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM LoongArchGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM LoongArchGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM LoongArchGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM LoongArchGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM LoongArchGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM LoongArchGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/M68k/CMakeLists.txt b/llvm/lib/Target/M68k/CMakeLists.txt
index 1661dccece3dd8..70856d123255cb 100644
--- a/llvm/lib/Target/M68k/CMakeLists.txt
+++ b/llvm/lib/Target/M68k/CMakeLists.txt
@@ -2,14 +2,14 @@ add_llvm_component_group(M68k)
set(LLVM_TARGET_DEFINITIONS M68k.td)
-tablegen(LLVM M68kGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM M68kGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM M68kGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM M68kGenRegisterBank.inc -gen-register-bank)
-tablegen(LLVM M68kGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM M68kGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM M68kGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM M68kGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
-tablegen(LLVM M68kGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM M68kGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM M68kGenCallingConv.inc -gen-callingconv)
tablegen(LLVM M68kGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM M68kGenAsmMatcher.inc -gen-asm-matcher)
diff --git a/llvm/lib/Target/MSP430/CMakeLists.txt b/llvm/lib/Target/MSP430/CMakeLists.txt
index 1dfe8635acb32b..6a8a9248f6577e 100644
--- a/llvm/lib/Target/MSP430/CMakeLists.txt
+++ b/llvm/lib/Target/MSP430/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS MSP430.td)
tablegen(LLVM MSP430GenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM MSP430GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM MSP430GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM MSP430GenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM MSP430GenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM MSP430GenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM MSP430GenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM MSP430GenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM MSP430GenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM MSP430GenRegisterInfo.inc -gen-register-info)
tablegen(LLVM MSP430GenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/Mips/CMakeLists.txt b/llvm/lib/Target/Mips/CMakeLists.txt
index 28f66a4ad94826..5bfadf0f317a11 100644
--- a/llvm/lib/Target/Mips/CMakeLists.txt
+++ b/llvm/lib/Target/Mips/CMakeLists.txt
@@ -5,13 +5,13 @@ set(LLVM_TARGET_DEFINITIONS Mips.td)
tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM MipsGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="MipsPostLegalizerCombiner")
-tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
diff --git a/llvm/lib/Target/NVPTX/CMakeLists.txt b/llvm/lib/Target/NVPTX/CMakeLists.txt
index 693365161330f5..fa9004a6c2978f 100644
--- a/llvm/lib/Target/NVPTX/CMakeLists.txt
+++ b/llvm/lib/Target/NVPTX/CMakeLists.txt
@@ -3,8 +3,8 @@ add_llvm_component_group(NVPTX)
set(LLVM_TARGET_DEFINITIONS NVPTX.td)
tablegen(LLVM NVPTXGenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM NVPTXGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM NVPTXGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM NVPTXGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM NVPTXGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM NVPTXGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM NVPTXGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt
index cd4c76013d2041..45adcccdcdc749 100644
--- a/llvm/lib/Target/PowerPC/CMakeLists.txt
+++ b/llvm/lib/Target/PowerPC/CMakeLists.txt
@@ -5,16 +5,16 @@ set(LLVM_TARGET_DEFINITIONS PPC.td)
tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM PPCGenExegesis.inc -gen-exegesis)
tablegen(LLVM PPCGenRegisterBank.inc -gen-register-bank)
-tablegen(LLVM PPCGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM PPCGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
add_public_tablegen_target(PowerPCCommonTableGen)
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index fd049d1a57860e..832496c6fcf8f0 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -6,9 +6,9 @@ tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
-tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
@@ -17,7 +17,7 @@ tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
-tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM RISCVGenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="RISCVO0PreLegalizerCombiner")
tablegen(LLVM RISCVGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/SPIRV/CMakeLists.txt b/llvm/lib/Target/SPIRV/CMakeLists.txt
index 326343ae278148..e4c4ccbe6ba949 100644
--- a/llvm/lib/Target/SPIRV/CMakeLists.txt
+++ b/llvm/lib/Target/SPIRV/CMakeLists.txt
@@ -3,8 +3,8 @@ add_llvm_component_group(SPIRV)
set(LLVM_TARGET_DEFINITIONS SPIRV.td)
tablegen(LLVM SPIRVGenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM SPIRVGenGlobalISel.inc -gen-global-isel)
-tablegen(LLVM SPIRVGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM SPIRVGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM SPIRVGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM SPIRVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SPIRVGenRegisterBank.inc -gen-register-bank)
tablegen(LLVM SPIRVGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/Sparc/CMakeLists.txt b/llvm/lib/Target/Sparc/CMakeLists.txt
index bf76ed9d671b97..abf0e3c264c6ff 100644
--- a/llvm/lib/Target/Sparc/CMakeLists.txt
+++ b/llvm/lib/Target/Sparc/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td)
tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM SparcGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM SparcGenSearchableTables.inc -gen-searchable-tables)
diff --git a/llvm/lib/Target/SystemZ/CMakeLists.txt b/llvm/lib/Target/SystemZ/CMakeLists.txt
index 063e5bcd44171e..2e81812b1f7da2 100644
--- a/llvm/lib/Target/SystemZ/CMakeLists.txt
+++ b/llvm/lib/Target/SystemZ/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS SystemZ.td)
tablegen(LLVM SystemZGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM SystemZGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM SystemZGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM SystemZGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/VE/CMakeLists.txt b/llvm/lib/Target/VE/CMakeLists.txt
index 76684d39450d8b..b4e43ef2080c11 100644
--- a/llvm/lib/Target/VE/CMakeLists.txt
+++ b/llvm/lib/Target/VE/CMakeLists.txt
@@ -3,12 +3,12 @@ add_llvm_component_group(VE)
set(LLVM_TARGET_DEFINITIONS VE.td)
tablegen(LLVM VEGenRegisterInfo.inc -gen-register-info)
-tablegen(LLVM VEGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM VEGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM VEGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM VEGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM VEGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM VEGenAsmMatcher.inc -gen-asm-matcher)
-tablegen(LLVM VEGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM VEGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM VEGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM VEGenCallingConv.inc -gen-callingconv)
add_public_tablegen_target(VECommonTableGen)
diff --git a/llvm/lib/Target/WebAssembly/CMakeLists.txt b/llvm/lib/Target/WebAssembly/CMakeLists.txt
index 1e83cbeac50d6d..9a5574ce0c561b 100644
--- a/llvm/lib/Target/WebAssembly/CMakeLists.txt
+++ b/llvm/lib/Target/WebAssembly/CMakeLists.txt
@@ -4,10 +4,10 @@ set(LLVM_TARGET_DEFINITIONS WebAssembly.td)
tablegen(LLVM WebAssemblyGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM WebAssemblyGenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM WebAssemblyGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM WebAssemblyGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM WebAssemblyGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM WebAssemblyGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM WebAssemblyGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM WebAssemblyGenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM WebAssemblyGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM WebAssemblyGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM WebAssemblyGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM WebAssemblyGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/X86/CMakeLists.txt b/llvm/lib/Target/X86/CMakeLists.txt
index 9553a8619feb51..2065dd118e7bfd 100644
--- a/llvm/lib/Target/X86/CMakeLists.txt
+++ b/llvm/lib/Target/X86/CMakeLists.txt
@@ -6,14 +6,15 @@ tablegen(LLVM X86GenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM X86GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM X86GenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM X86GenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM X86GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM X86GenInstrMapping.inc -gen-x86-instr-mapping)
tablegen(LLVM X86GenExegesis.inc -gen-exegesis)
-tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)
-tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM X86GenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM X86GenInstrInfo.inc -gen-instr-info
- -instr-info-expand-mi-operand-info=0)
+ -instr-info-expand-mi-operand-info=0
+ ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM X86GenMnemonicTables.inc -gen-x86-mnemonic-tables -asmwriternum=1)
tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
tablegen(LLVM X86GenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/XCore/CMakeLists.txt b/llvm/lib/Target/XCore/CMakeLists.txt
index 447f5c54528850..54a55c4a42a422 100644
--- a/llvm/lib/Target/XCore/CMakeLists.txt
+++ b/llvm/lib/Target/XCore/CMakeLists.txt
@@ -4,9 +4,9 @@ set(LLVM_TARGET_DEFINITIONS XCore.td)
tablegen(LLVM XCoreGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM XCoreGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM XCoreGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM XCoreGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt
index 726efadc87c0b2..5d3dd7b09e7308 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS Xtensa.td)
tablegen(LLVM XtensaGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM XtensaGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM XtensaGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM XtensaGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM XtensaGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM XtensaGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM XtensaGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll b/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
index 905e7eea9f49ee..5734fc65e14fec 100644
--- a/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
+++ b/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
@@ -1,4 +1,5 @@
; REQUIRES: x86_64-linux
+; REQUIRES: x86-registered-target
;
; RUN: rm -rf %t
; RUN: split-file %s %t
diff --git a/llvm/test/Analysis/DXILResource/buffer-frombinding.ll b/llvm/test/Analysis/DXILResource/buffer-frombinding.ll
index b26a185423597d..ece1e7b60e6d14 100644
--- a/llvm/test/Analysis/DXILResource/buffer-frombinding.ll
+++ b/llvm/test/Analysis/DXILResource/buffer-frombinding.ll
@@ -1,3 +1,4 @@
+; REQUIRES: dx-registered-target
; RUN: opt -S -disable-output -passes="print<dxil-resource>" < %s 2>&1 | FileCheck %s
@G = external constant <4 x float>, align 4
diff --git a/llvm/test/Analysis/MemorySSA/pr36883.ll b/llvm/test/Analysis/MemorySSA/pr36883.ll
index 329026beb2895d..0a1c0b600ec1de 100644
--- a/llvm/test/Analysis/MemorySSA/pr36883.ll
+++ b/llvm/test/Analysis/MemorySSA/pr36883.ll
@@ -1,3 +1,4 @@
+; REQUIRES: arm-registered-target
; RUN: opt -aa-pipeline=basic-aa -passes='print<memoryssa>,verify<memoryssa>' -S < %s 2>&1 | FileCheck %s
;
; We weren't properly considering the args in callsites in equality or hashing.
diff --git a/llvm/test/Analysis/ValueTracking/aarch64.irg.ll b/llvm/test/Analysis/ValueTracking/aarch64.irg.ll
index cef2e9edff3409..8db930373702cd 100644
--- a/llvm/test/Analysis/ValueTracking/aarch64.irg.ll
+++ b/llvm/test/Analysis/ValueTracking/aarch64.irg.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: opt -S -passes=instsimplify,instcombine < %s | FileCheck %s
; CHECK-LABEL: define void @checkNonnullIrg()
diff --git a/llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll b/llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll
index e2fe873d715cd6..d41033b2a33aca 100644
--- a/llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll
+++ b/llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; REQUIRES: x86-registered-target
; RUN: opt -S -passes=instcombine < %s | FileCheck %s
define <4 x i1> @hadd_and_eq_v4i32(<4 x i32> %x, <4 x i32> %y) {
diff --git a/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll b/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
index bc03908d5f218b..abe06c6fd872f7 100644
--- a/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
+++ b/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
@@ -1,3 +1,4 @@
+; REQUIRES: amdgpu-registered-target
; RUN: opt -S -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s
define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
diff --git a/llvm/test/Assembler/autoupgrade-wasm-intrinsics.ll b/llvm/test/Assembler/autoupgrade-wasm-intrinsics.ll
index 012fa1dfe7e281..89674ff5dc8a41 100644
--- a/llvm/test/Assembler/autoupgrade-wasm-intrinsics.ll
+++ b/llvm/test/Assembler/autoupgrade-wasm-intrinsics.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; REQUIRES: wasm-registered-target
; RUN: opt -S < %s | FileCheck %s
define <16 x i8> @test_laneselect(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
diff --git a/llvm/test/Assembler/opaque-ptr-intrinsic-remangling.ll b/llvm/test/Assembler/opaque-ptr-intrinsic-remangling.ll
index 070bcd40438df2..431f00a1843371 100644
--- a/llvm/test/Assembler/opaque-ptr-intrinsic-remangling.ll
+++ b/llvm/test/Assembler/opaque-ptr-intrinsic-remangling.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; REQUIRES: wasm-registered-target
; RUN: opt -S < %s | FileCheck %s
; Make sure that opaque pointer intrinsic remangling upgrade works.
diff --git a/llvm/test/Bitcode/aarch64-addp-upgrade.ll b/llvm/test/Bitcode/aarch64-addp-upgrade.ll
index 4e78996aa0b636..29c36edfe41602 100644
--- a/llvm/test/Bitcode/aarch64-addp-upgrade.ll
+++ b/llvm/test/Bitcode/aarch64-addp-upgrade.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-dis %p/aarch64-addp-upgrade.bc -o - | FileCheck %s
; Bitcode was generated from file below, which may or may not even assemble any
diff --git a/llvm/test/Bitcode/aarch64-bf16-upgrade.ll b/llvm/test/Bitcode/aarch64-bf16-upgrade.ll
index a1ae9f172994d0..d888df03c14817 100644
--- a/llvm/test/Bitcode/aarch64-bf16-upgrade.ll
+++ b/llvm/test/Bitcode/aarch64-bf16-upgrade.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-dis < %s.bc | FileCheck %s
; Bitcode was generated from file below
diff --git a/llvm/test/Bitcode/arm-bf16-upgrade.ll b/llvm/test/Bitcode/arm-bf16-upgrade.ll
index a8ee8e4ac7e50b..f7b4d09d63e563 100644
--- a/llvm/test/Bitcode/arm-bf16-upgrade.ll
+++ b/llvm/test/Bitcode/arm-bf16-upgrade.ll
@@ -1,3 +1,4 @@
+; REQUIRES: arm-registered-target
; RUN: llvm-dis < %s.bc | FileCheck %s
; Bitcode was generated from file below
diff --git a/llvm/test/Bitcode/arm-intrinsics.ll b/llvm/test/Bitcode/arm-intrinsics.ll
index be52c59b5518b5..c22421937f1138 100644
--- a/llvm/test/Bitcode/arm-intrinsics.ll
+++ b/llvm/test/Bitcode/arm-intrinsics.ll
@@ -1,3 +1,4 @@
+; REQUIRES: arm-registered-target
; RUN: llvm-dis < %S/arm-intrinsics.bc | FileCheck %s
define void @f(i32* %p) {
diff --git a/llvm/test/Bitcode/intrinsics-struct-upgrade-attributes.ll b/llvm/test/Bitcode/intrinsics-struct-upgrade-attributes.ll
index 4962144899ae4b..6d98d34edd81aa 100644
--- a/llvm/test/Bitcode/intrinsics-struct-upgrade-attributes.ll
+++ b/llvm/test/Bitcode/intrinsics-struct-upgrade-attributes.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
diff --git a/llvm/test/Bitcode/intrinsics-struct-upgrade.ll b/llvm/test/Bitcode/intrinsics-struct-upgrade.ll
index e7e944ed131215..bc9adf2ecb9658 100644
--- a/llvm/test/Bitcode/intrinsics-struct-upgrade.ll
+++ b/llvm/test/Bitcode/intrinsics-struct-upgrade.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-dis < %s.bc | FileCheck %s
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
diff --git a/llvm/test/Bitcode/ptest-new.ll b/llvm/test/Bitcode/ptest-new.ll
index 952ea795d62fb5..ab2383694761f2 100644
--- a/llvm/test/Bitcode/ptest-new.ll
+++ b/llvm/test/Bitcode/ptest-new.ll
@@ -1,4 +1,5 @@
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; REQUIRES: x86-registered-target
; RUN: verify-uselistorder < %s
define i32 @foo(<2 x i64> %bar) nounwind {
diff --git a/llvm/test/Bitcode/upgrade-aarch64-ldstxr.ll b/llvm/test/Bitcode/upgrade-aarch64-ldstxr.ll
index cd5f32ec68e4e5..714b1e8a789fb1 100644
--- a/llvm/test/Bitcode/upgrade-aarch64-ldstxr.ll
+++ b/llvm/test/Bitcode/upgrade-aarch64-ldstxr.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-dis < %S/upgrade-aarch64-ldstxr.bc | FileCheck %s
define void @f(i32* %p) {
diff --git a/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll b/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
index a2d171c173089f..e9610a83a4a958 100644
--- a/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
+++ b/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-as %s -o - | llvm-dis - | FileCheck %s
define <vscale x 32 x i8> @ld2.nxv32i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr) {
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index 1dfd977186b0e7..bbecef7397f97c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; REQUIRES: aarch64-registered-target
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -enable-misched=false | FileCheck %s
define <8 x i8> @sqshl8b(ptr %A, ptr %B) nounwind {
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
index 4cc038f03ff2c3..5ca11cc0ca6630 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool opt --version 4
;
+; REQUIRES: aarch64-registered-target
; RUN: opt < %s -passes=msan -S | FileCheck %s
;
; Forked from llvm/test/CodeGen/AArch64/arm64-vshift.ll
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
index 421f00fcbc56bf..01a38af2fb7ad5 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; Test memory sanitizer instrumentation for Arm NEON VST instructions.
;
+; REQUIRES: aarch64-registered-target
; RUN: opt < %s -passes=msan -S | FileCheck %s
;
; Forked from llvm/test/CodeGen/AArch64/arm64-st1.ll
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_float.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_float.ll
index 8fed5a78d6b79f..cd2bb501837e6b 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_float.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_float.ll
@@ -3,6 +3,7 @@
; Test memory sanitizer instrumentation for Arm NEON VST_{2,3,4} and
; VST_1x{2,3,4} instructions, including floating-point parameters.
;
+; REQUIRES: aarch64-registered-target
; RUN: opt < %s -passes=msan -S | FileCheck %s
;
; Generated with:
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
index 9ed364df3e677f..6e888531653e8c 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
@@ -3,6 +3,7 @@
; Test memory sanitizer instrumentation for Arm store with lane instructions.
; Note: st{2,3,4}lane uses Arm NEON but st1lane does not.
;
+; REQUIRES: aarch64-registered-target
; RUN: opt < %s -passes=msan -S | FileCheck %s
;
; Forked from llvm/test/CodeGen/AArch64/arm64-st1.ll
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_origins.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_origins.ll
index 52283811e30653..2791b1f9588d71 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_origins.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_origins.ll
@@ -3,6 +3,7 @@
; origin tracking. These tests are deliberately shorter than neon_vst.ll, due
; to the verbosity of the output.
;
+; REQUIRES: aarch64-registered-target
; RUN: opt < %s -passes=msan -msan-track-origins=2 -S | FileCheck %s
;
; Forked from llvm/test/CodeGen/AArch64/arm64-st1.ll
diff --git a/llvm/test/TableGen/ContextlessPredicates.td b/llvm/test/TableGen/ContextlessPredicates.td
index eead9655111e68..d80da7b8d633a8 100644
--- a/llvm/test/TableGen/ContextlessPredicates.td
+++ b/llvm/test/TableGen/ContextlessPredicates.td
@@ -1,6 +1,6 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK_NOPT -input-file=%T/context-non-optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/context-optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/context-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK_OPT -input-file=%T/context-optimized.cpp
diff --git a/llvm/test/TableGen/DAGDefaultOps.td b/llvm/test/TableGen/DAGDefaultOps.td
index 70c8413f2c053a..0ff4b8828a6039 100644
--- a/llvm/test/TableGen/DAGDefaultOps.td
+++ b/llvm/test/TableGen/DAGDefaultOps.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s -o %t
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s -o %t
// RUN: FileCheck --check-prefix=ADD %s < %t
// RUN: FileCheck --check-prefix=ADDINT %s < %t
// RUN: FileCheck --check-prefix=SUB %s < %t
diff --git a/llvm/test/TableGen/DefaultOpsGlobalISel.td b/llvm/test/TableGen/DefaultOpsGlobalISel.td
index 8f4176a2aa730b..5dc2e0645f1be2 100644
--- a/llvm/test/TableGen/DefaultOpsGlobalISel.td
+++ b/llvm/test/TableGen/DefaultOpsGlobalISel.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/DuplicateFieldValues.td b/llvm/test/TableGen/DuplicateFieldValues.td
index 50c77fa88ccecc..d07bb121a73d39 100644
--- a/llvm/test/TableGen/DuplicateFieldValues.td
+++ b/llvm/test/TableGen/DuplicateFieldValues.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-instr-info --enabled-targets=all -I %p/../../include %s | FileCheck %s
// CHECK: ABCForm_A
// CHECK-NOT: ABCForm_A
diff --git a/llvm/test/TableGen/FastISelEmitter.td b/llvm/test/TableGen/FastISelEmitter.td
index d5fea8dd1e0c0d..980601afa036f3 100644
--- a/llvm/test/TableGen/FastISelEmitter.td
+++ b/llvm/test/TableGen/FastISelEmitter.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen --gen-fast-isel -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: llvm-tblgen --gen-fast-isel --enabled-targets=all -I %p/../../include %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-PR39045.td b/llvm/test/TableGen/GlobalISelEmitter-PR39045.td
index 5407222121bb3a..6ee7e286d8da14 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-PR39045.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-PR39045.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %t
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -o %t
// RUN: FileCheck %s < %t
// Both predicates should be tested
diff --git a/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td b/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
index 8d6dedf2f920ce..f1eb32e8c96061 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td b/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
index da2dfe8004289d..1aaa6368a51252 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-frameindex.td b/llvm/test/TableGen/GlobalISelEmitter-frameindex.td
index 232691465bb3bd..6b449661bba9df 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-frameindex.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-frameindex.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td b/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
index 0125aa5c30fa6d..6c6a4171620894 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT %s
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td b/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
index 6b4012eb736cb3..786593828e9204 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-input-discard.td b/llvm/test/TableGen/GlobalISelEmitter-input-discard.td
index 202ff4a5758d7f..cba89728452ee6 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-input-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-input-discard.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
index 2d968bebbc65e0..9c2c2aac4d6e6b 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td b/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
index dea3b549607170..ea9545301a273e 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
index 25a39a40da6188..3c26d2785b385f 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false --enabled-targets=all -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td b/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
index 622d7fa1f7955c..55017117409498 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter-output-discard.td
index 7a0242d9a99243..bad3524c0bb2fd 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-output-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-output-discard.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-setcc.td b/llvm/test/TableGen/GlobalISelEmitter-setcc.td
index 38add7627f5030..b72341f6d16989 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-setcc.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-setcc.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s
// RUN: FileCheck -DFILE=%s -check-prefix=ERR %s < %t
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td b/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
index c8a8cab2b65232..71fe36caa85257 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td b/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
index ddf02240ee1f8b..47b5b1ef367906 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td
index 7dbaf4390c0f70..9169aa73e59a78 100644
--- a/llvm/test/TableGen/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter.td
@@ -1,6 +1,6 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %T/default.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -o %T/default.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19N -input-file=%T/non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19O -input-file=%T/optimized.cpp
diff --git a/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td b/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
index 3ceadf32f06425..0f18c72e3d9f92 100644
--- a/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
+++ b/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
// Verify that all MI predicates are enumerated.
//
diff --git a/llvm/test/TableGen/GlobalISelEmitterFlags.td b/llvm/test/TableGen/GlobalISelEmitterFlags.td
index fa8f2a79fbce89..001d48a1abe8c8 100644
--- a/llvm/test/TableGen/GlobalISelEmitterFlags.td
+++ b/llvm/test/TableGen/GlobalISelEmitterFlags.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterHwModes.td b/llvm/test/TableGen/GlobalISelEmitterHwModes.td
index 9d235f5f07a74b..c8df4f46ff8807 100644
--- a/llvm/test/TableGen/GlobalISelEmitterHwModes.td
+++ b/llvm/test/TableGen/GlobalISelEmitterHwModes.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/hwmode-non-optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/hwmode-non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK -input-file=%T/hwmode-non-optimized.cpp
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
index 3db31bea8612ee..ca71ec41bd4db8 100644
--- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
+++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
index d93805b612a19e..d612f3e5c29e47 100644
--- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
+++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td
index 1ac33990ab3b10..a2a2a8b6da07ec 100644
--- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td
+++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td b/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
index 422edbba0e7a0f..49c024a22425d4 100644
--- a/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
+++ b/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -o - | FileCheck %s
// Boilerplate code.
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterRegSequence.td b/llvm/test/TableGen/GlobalISelEmitterRegSequence.td
index 3829070b28efeb..019f279d3fed4a 100644
--- a/llvm/test/TableGen/GlobalISelEmitterRegSequence.td
+++ b/llvm/test/TableGen/GlobalISelEmitterRegSequence.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
index fc8abc6fbc547e..5c4808b44d61c9 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
-// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null -DIGNORE 2>&1 | FileCheck --allow-empty --check-prefix=IGNORED %s
+// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel --enabled-targets=all -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel --enabled-targets=all -I %p/../../include %s -I %p/Common -o /dev/null -DIGNORE 2>&1 | FileCheck --allow-empty --check-prefix=IGNORED %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterSubreg.td b/llvm/test/TableGen/GlobalISelEmitterSubreg.td
index 8df3238f6cc21e..8d2796dd4f1707 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSubreg.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSubreg.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common -o - 2> %t.skipped | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -I %p/../../include -I %p/Common -o - 2> %t.skipped | FileCheck %s
// RUN: cat %t.skipped | FileCheck %s --check-prefix=SKIPPED
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterVariadic.td b/llvm/test/TableGen/GlobalISelEmitterVariadic.td
index 992e1a4b907c30..630c7b501b813b 100644
--- a/llvm/test/TableGen/GlobalISelEmitterVariadic.td
+++ b/llvm/test/TableGen/GlobalISelEmitterVariadic.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/HasNoUse.td b/llvm/test/TableGen/HasNoUse.td
index 6e6bcc2a81df70..24965f7e2bf524 100644
--- a/llvm/test/TableGen/HasNoUse.td
+++ b/llvm/test/TableGen/HasNoUse.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=SDAG %s
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=SDAG %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/RelTest.td b/llvm/test/TableGen/RelTest.td
index dc8b4e559f1904..7bf04578006755 100644
--- a/llvm/test/TableGen/RelTest.td
+++ b/llvm/test/TableGen/RelTest.td
@@ -1,4 +1,4 @@
-// RUN: not llvm-tblgen -gen-instr-info -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: not llvm-tblgen -gen-instr-info --enabled-targets=all -I %p/../../include %s 2>&1 | FileCheck %s
// This test verifies that TableGen is displaying an error when mapped instruction
// does not contain a field listed under RowFields.
diff --git a/llvm/test/TableGen/address-space-patfrags.td b/llvm/test/TableGen/address-space-patfrags.td
index 582b97d55a5185..da422c456111c3 100644
--- a/llvm/test/TableGen/address-space-patfrags.td
+++ b/llvm/test/TableGen/address-space-patfrags.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck -check-prefix=SDAG %s
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s 2>&1 | FileCheck -check-prefix=SDAG %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/dag-isel-complexpattern.td b/llvm/test/TableGen/dag-isel-complexpattern.td
index b8f517a1fc2890..704724c8302c70 100644
--- a/llvm/test/TableGen/dag-isel-complexpattern.td
+++ b/llvm/test/TableGen/dag-isel-complexpattern.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
index c41a19e97e763d..de2153ce6c51f5 100644
--- a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+++ b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/dag-isel-res-order.td b/llvm/test/TableGen/dag-isel-res-order.td
index 6937dd8c6b807c..e025ac51afb55f 100644
--- a/llvm/test/TableGen/dag-isel-res-order.td
+++ b/llvm/test/TableGen/dag-isel-res-order.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/dag-isel-subregs.td b/llvm/test/TableGen/dag-isel-subregs.td
index 52ac0377bd2c9f..6a11b435a937c0 100644
--- a/llvm/test/TableGen/dag-isel-subregs.td
+++ b/llvm/test/TableGen/dag-isel-subregs.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common %s | FileCheck %s
include "reg-with-subregs-common.td"
diff --git a/llvm/test/TableGen/def-multiple-operands.td b/llvm/test/TableGen/def-multiple-operands.td
index b747c58907505a..b20a4d63871acb 100644
--- a/llvm/test/TableGen/def-multiple-operands.td
+++ b/llvm/test/TableGen/def-multiple-operands.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-instr-info --enabled-targets=all -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/get-operand-type-no-expand.td b/llvm/test/TableGen/get-operand-type-no-expand.td
index 9dfcbfaec76af1..d090675877682d 100644
--- a/llvm/test/TableGen/get-operand-type-no-expand.td
+++ b/llvm/test/TableGen/get-operand-type-no-expand.td
@@ -30,7 +30,7 @@ def InstA : Instruction {
}
// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s \
-// RUN: -instr-info-expand-mi-operand-info=1 \
+// RUN: -instr-info-expand-mi-operand-info=1 --enabled-targets=all \
// RUN: | FileCheck %s --check-prefix=CHECK-EXPAND
// CHECK-EXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE
// CHECK-EXPAND: OpcodeOperandTypes[] = {
@@ -39,7 +39,7 @@ def InstA : Instruction {
// CHECK-EXPAND: #endif // GET_INSTRINFO_OPERAND_TYPE
// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s \
-// RUN: -instr-info-expand-mi-operand-info=0 \
+// RUN: -instr-info-expand-mi-operand-info=0 --enabled-targets=all \
// RUN: | FileCheck %s --check-prefix=CHECK-NOEXPAND
// CHECK-NOEXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE
// CHECK-NOEXPAND: OpcodeOperandTypes[] = {
diff --git a/llvm/test/TableGen/get-operand-type.td b/llvm/test/TableGen/get-operand-type.td
index 6ebda5cffe8af0..438ce5fa243981 100644
--- a/llvm/test/TableGen/get-operand-type.td
+++ b/llvm/test/TableGen/get-operand-type.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-instr-info --enabled-targets=all -I %p/../../include %s | FileCheck %s
// Check that getOperandType has the expected info in it
diff --git a/llvm/test/TableGen/gisel-physreg-input.td b/llvm/test/TableGen/gisel-physreg-input.td
index f19872a331fc89..1a707db28a8b86 100644
--- a/llvm/test/TableGen/gisel-physreg-input.td
+++ b/llvm/test/TableGen/gisel-physreg-input.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/immarg-predicated.td b/llvm/test/TableGen/immarg-predicated.td
index dcacb2f8f1de35..896e8834b2708d 100644
--- a/llvm/test/TableGen/immarg-predicated.td
+++ b/llvm/test/TableGen/immarg-predicated.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/immarg.td b/llvm/test/TableGen/immarg.td
index e5fd06ce6c083f..0e501cd0a7cf4f 100644
--- a/llvm/test/TableGen/immarg.td
+++ b/llvm/test/TableGen/immarg.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/intrinsic-attrs.td b/llvm/test/TableGen/intrinsic-attrs.td
index 579b5e8a21b868..bebeadd291ae7c 100644
--- a/llvm/test/TableGen/intrinsic-attrs.td
+++ b/llvm/test/TableGen/intrinsic-attrs.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-intrinsic-impl -I %p/../../include -DTEST_INTRINSICS_SUPPRESS_DEFS %s | FileCheck %s
+// RUN: llvm-tblgen -gen-intrinsic-impl --enabled-targets=all -I %p/../../include -DTEST_INTRINSICS_SUPPRESS_DEFS %s | FileCheck %s
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-duplicate-name.td b/llvm/test/TableGen/intrinsic-duplicate-name.td
index 64d94d3192541d..acb60a0ffba075 100644
--- a/llvm/test/TableGen/intrinsic-duplicate-name.td
+++ b/llvm/test/TableGen/intrinsic-duplicate-name.td
@@ -1,4 +1,4 @@
-// RUN: not llvm-tblgen -gen-intrinsic-impl -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not llvm-tblgen -gen-intrinsic-impl --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS 2>&1 | FileCheck %s -DFILE=%s
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-long-name.td b/llvm/test/TableGen/intrinsic-long-name.td
index c19910d474ed10..224d9f988f5cc5 100644
--- a/llvm/test/TableGen/intrinsic-long-name.td
+++ b/llvm/test/TableGen/intrinsic-long-name.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-intrinsic-enums -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
+// RUN: llvm-tblgen -gen-intrinsic-enums --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
// XFAIL: vg_leak
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-overload-conflict.td b/llvm/test/TableGen/intrinsic-overload-conflict.td
index 84333119d41f53..40101699d5d964 100644
--- a/llvm/test/TableGen/intrinsic-overload-conflict.td
+++ b/llvm/test/TableGen/intrinsic-overload-conflict.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-intrinsic-enums -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
-// RUN: not llvm-tblgen -gen-intrinsic-enums -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS -DCONFLICT 2>&1 | FileCheck %s -DFILE=%s --check-prefix=CHECK-CONFLICT
+// RUN: llvm-tblgen -gen-intrinsic-enums --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
+// RUN: not llvm-tblgen -gen-intrinsic-enums --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS -DCONFLICT 2>&1 | FileCheck %s -DFILE=%s --check-prefix=CHECK-CONFLICT
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-prefix-error.td b/llvm/test/TableGen/intrinsic-prefix-error.td
index 3869bde3a4ba76..ef05c59222ff48 100644
--- a/llvm/test/TableGen/intrinsic-prefix-error.td
+++ b/llvm/test/TableGen/intrinsic-prefix-error.td
@@ -1,4 +1,4 @@
-// RUN: not llvm-tblgen -gen-intrinsic-enums --intrinsic-prefix=gen3 -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS 2>&1 | FileCheck %s
+// RUN: not llvm-tblgen -gen-intrinsic-enums --enabled-targets=all --intrinsic-prefix=gen3 -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS 2>&1 | FileCheck %s
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-struct.td b/llvm/test/TableGen/intrinsic-struct.td
index 467fd9057c1833..3df345f4830bf8 100644
--- a/llvm/test/TableGen/intrinsic-struct.td
+++ b/llvm/test/TableGen/intrinsic-struct.td
@@ -1,6 +1,6 @@
-// RUN: llvm-tblgen -gen-intrinsic-enums -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s --check-prefix=CHECK-ENUM
-// RUN: llvm-tblgen -gen-intrinsic-impl -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS > /dev/null 2>&1
-// RUN: not llvm-tblgen -gen-intrinsic-impl -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS -DENABLE_ERROR 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-tblgen -gen-intrinsic-enums --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s --check-prefix=CHECK-ENUM
+// RUN: llvm-tblgen -gen-intrinsic-impl --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS > /dev/null 2>&1
+// RUN: not llvm-tblgen -gen-intrinsic-impl --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS -DENABLE_ERROR 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
// XFAIL: vg_leak
diff --git a/llvm/test/TableGen/intrinsic-target-prefix-for-target-independent.td b/llvm/test/TableGen/intrinsic-target-prefix-for-target-independent.td
index 84e365f02d968c..ce770bf97b5eb3 100644
--- a/llvm/test/TableGen/intrinsic-target-prefix-for-target-independent.td
+++ b/llvm/test/TableGen/intrinsic-target-prefix-for-target-independent.td
@@ -1,4 +1,4 @@
-// RUN: not llvm-tblgen -gen-intrinsic-enums -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not llvm-tblgen -gen-intrinsic-enums --enabled-targets=all -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-varargs.td b/llvm/test/TableGen/intrinsic-varargs.td
index 3634e16e205653..ccc29c9758a982 100644
--- a/llvm/test/TableGen/intrinsic-varargs.td
+++ b/llvm/test/TableGen/intrinsic-varargs.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-intrinsic-impl -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
+// RUN: llvm-tblgen -gen-intrinsic-impl --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
// XFAIL: vg_leak
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/invalid-type-cast-patfrags.td b/llvm/test/TableGen/invalid-type-cast-patfrags.td
index 49d8a73b810788..02a82636e28088 100644
--- a/llvm/test/TableGen/invalid-type-cast-patfrags.td
+++ b/llvm/test/TableGen/invalid-type-cast-patfrags.td
@@ -1,7 +1,7 @@
-// RUN: not llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
-// RUN: not llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common -DERROR2 %s 2>&1 | FileCheck --check-prefix=ERROR2 %s
-// RUN: not llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common -DERROR3 %s 2>&1 | FileCheck --check-prefix=ERROR3 %s
-// RUN: not llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common -DERROR4 %s 2>&1 | FileCheck --check-prefix=ERROR4 %s
+// RUN: not llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
+// RUN: not llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common -DERROR2 %s 2>&1 | FileCheck --check-prefix=ERROR2 %s
+// RUN: not llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common -DERROR3 %s 2>&1 | FileCheck --check-prefix=ERROR3 %s
+// RUN: not llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common -DERROR4 %s 2>&1 | FileCheck --check-prefix=ERROR4 %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/multiple-type-casts-patfrags.td b/llvm/test/TableGen/multiple-type-casts-patfrags.td
index c4b4b62995fdb3..93d0429b1cb613 100644
--- a/llvm/test/TableGen/multiple-type-casts-patfrags.td
+++ b/llvm/test/TableGen/multiple-type-casts-patfrags.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck -check-prefix=SDAG %s
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common %s | FileCheck -check-prefix=SDAG %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/predicate-patfags.td b/llvm/test/TableGen/predicate-patfags.td
index 39133f324f305d..98fc6d5341f5d5 100644
--- a/llvm/test/TableGen/predicate-patfags.td
+++ b/llvm/test/TableGen/predicate-patfags.td
@@ -1,7 +1,7 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefixes=SDAG,SCUSTOM %s
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s -DHASONEUSE 2>&1 | FileCheck -check-prefixes=SDAG,SBUILTIN %s
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefixes=GISEL,GCUSTOM %s
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -DHASONEUSE 2>&1 | FileCheck -check-prefixes=GISEL,GBUILTIN %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefixes=SDAG,SCUSTOM %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -DHASONEUSE 2>&1 | FileCheck -check-prefixes=SDAG,SBUILTIN %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefixes=GISEL,GCUSTOM %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -DHASONEUSE 2>&1 | FileCheck -check-prefixes=GISEL,GBUILTIN %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/simplify-patfrag.td b/llvm/test/TableGen/simplify-patfrag.td
index fbb6f97f286311..b6bb6bc41226f6 100644
--- a/llvm/test/TableGen/simplify-patfrag.td
+++ b/llvm/test/TableGen/simplify-patfrag.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -DIGNORE %s 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -DIGNORE %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
index 2a246d60de6156..9b4c4fdb7ce4aa 100644
--- a/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
+++ b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
@@ -13,7 +13,9 @@
#include "CodeGenIntrinsics.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/Twine.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
@@ -21,6 +23,11 @@
#include <cassert>
using namespace llvm;
+cl::list<std::string> EnabledTargets(
+ "enabled-targets", cl::CommaSeparated,
+ cl::desc("Targets prefixes for enabled targets"),
+ cl::value_desc("set of target prefixes for targets that are enabled"));
+
//===----------------------------------------------------------------------===//
// CodeGenIntrinsic Implementation
//===----------------------------------------------------------------------===//
@@ -49,22 +56,47 @@ CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) {
for (const Record *Def : Defs)
Intrinsics.emplace_back(CodeGenIntrinsic(Def, Ctx));
- llvm::sort(Intrinsics,
- [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
- // Order target independent intrinsics before target dependent
- // ones.
- bool LHSHasTarget = !LHS.TargetPrefix.empty();
- bool RHSHasTarget = !RHS.TargetPrefix.empty();
+ if (EnabledTargets.empty())
+ PrintFatalError("Enabled targets not specified");
+
+ StringSet<> EnabledTargetsSet(EnabledTargets);
- // To ensure deterministic sorted order when duplicates are
- // present, use record ID as a tie-breaker similar to
- // sortAndReportDuplicates in Utils.cpp.
- unsigned LhsID = LHS.TheDef->getID();
- unsigned RhsID = RHS.TheDef->getID();
+ const bool AllEnabled = EnabledTargetsSet.contains("all");
+ if (AllEnabled && EnabledTargets.size() > 1)
+ PrintFatalError(
+ "Additional enabled targets cannot be specified with 'all'");
- return std::tie(LHSHasTarget, LHS.Name, LhsID) <
- std::tie(RHSHasTarget, RHS.Name, RhsID);
- });
+ if (EnabledTargetsSet.contains("none")) {
+ if (EnabledTargets.size() > 1)
+ PrintFatalError(
+ "Additional enabled targets cannot be specified with 'none'");
+ EnabledTargetsSet.clear();
+ }
+
+ llvm::sort(Intrinsics, [&EnabledTargetsSet,
+ AllEnabled](const CodeGenIntrinsic &LHS,
+ const CodeGenIntrinsic &RHS) {
+ // Order target independent intrinsics before target dependent ones.
+ bool LHSHasTarget = !LHS.TargetPrefix.empty();
+ bool RHSHasTarget = !RHS.TargetPrefix.empty();
+
+ // Sort enabled targets before disabled ones. Target independent ones are
+ // always considered enabled. If no --enabled-targets option is provided,
+ // all of them are enabled by default.
+ bool LHSIsDisabled = LHSHasTarget && !AllEnabled &&
+ !EnabledTargetsSet.contains(LHS.TargetPrefix);
+ bool RHSIsDisabled = RHSHasTarget && !AllEnabled &&
+ !EnabledTargetsSet.contains(RHS.TargetPrefix);
+
+ // To ensure deterministic sorted order when duplicates are
+ // present, use record ID as a tie-breaker similar to
+ // sortAndReportDuplicates in Utils.cpp.
+ unsigned LhsID = LHS.TheDef->getID();
+ unsigned RhsID = RHS.TheDef->getID();
+
+ return std::tie(LHSHasTarget, LHSIsDisabled, LHS.Name, LhsID) <
+ std::tie(RHSHasTarget, RHSIsDisabled, RHS.Name, RhsID);
+ });
Targets.push_back({"", 0, 0});
for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
@@ -73,12 +105,40 @@ CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) {
Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
}
Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
+ NumEnabledTargets =
+ AllEnabled ? Targets.size() : EnabledTargetsSet.size() + 1;
+
+ // Verify that all targets provided on the command line were valid.
+ if (!AllEnabled) {
+ ArrayRef<TargetSet> KnowTargets = getAllTargets().drop_front();
+ for (const TargetSet &T : KnowTargets)
+ EnabledTargetsSet.erase(T.Name);
+
+ if (!EnabledTargetsSet.empty()) {
+ PrintFatalError([&EnabledTargetsSet, KnowTargets](raw_ostream &OS) {
+ OS << "Unknown enabled targets: ";
+ interleaveComma(EnabledTargetsSet, OS,
+ [&OS](const auto &Entry) { OS << Entry.first(); });
+ OS << "\nKnown targets are: ";
+ interleaveComma(KnowTargets, OS,
+ [&OS](const TargetSet &Target) { OS << Target.Name; });
+ OS << '\n';
+ });
+ }
+ }
+
+ const TargetSet &LastEnabledTarget = getEnabledTargets().back();
+ NumEnabledIntrinsics = LastEnabledTarget.Offset + LastEnabledTarget.Count;
CheckDuplicateIntrinsics();
CheckTargetIndependentIntrinsics();
CheckOverloadSuffixConflicts();
}
+ArrayRef<std::string> CodeGenIntrinsicTable::getEnabledCommandLineTargets() {
+ return EnabledTargets;
+}
+
// Check for duplicate intrinsic names.
void CodeGenIntrinsicTable::CheckDuplicateIntrinsics() const {
// Since the Intrinsics vector is already sorted by name, if there are 2 or
diff --git a/llvm/utils/TableGen/Basic/CodeGenIntrinsics.h b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
index 8428d09a94009e..1947ac15974120 100644
--- a/llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
+++ b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
@@ -178,17 +178,24 @@ class CodeGenIntrinsicTable {
explicit CodeGenIntrinsicTable(const RecordKeeper &RC);
- bool empty() const { return Intrinsics.empty(); }
- size_t size() const { return Intrinsics.size(); }
- auto begin() const { return Intrinsics.begin(); }
- auto end() const { return Intrinsics.end(); }
const CodeGenIntrinsic &operator[](size_t Pos) const {
return Intrinsics[Pos];
}
ArrayRef<CodeGenIntrinsic> operator[](const TargetSet &Set) const {
return ArrayRef(&Intrinsics[Set.Offset], Set.Count);
}
- ArrayRef<TargetSet> getTargets() const { return Targets; }
+ ArrayRef<CodeGenIntrinsic> getAllIntrinsics() const {
+ return ArrayRef(Intrinsics);
+ }
+ ArrayRef<CodeGenIntrinsic> getEnabledIntrinsics() const {
+ return getAllIntrinsics().take_front(NumEnabledIntrinsics);
+ }
+
+ ArrayRef<TargetSet> getAllTargets() const { return Targets; }
+ ArrayRef<TargetSet> getEnabledTargets() const {
+ return getAllTargets().take_front(NumEnabledTargets);
+ }
+ static ArrayRef<std::string> getEnabledCommandLineTargets();
private:
void CheckDuplicateIntrinsics() const;
@@ -197,6 +204,8 @@ class CodeGenIntrinsicTable {
std::vector<CodeGenIntrinsic> Intrinsics;
std::vector<TargetSet> Targets;
+ unsigned NumEnabledTargets = 0;
+ unsigned NumEnabledIntrinsics = 0;
};
// This class builds `CodeGenIntrinsic` on demand for a given Def.
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 1da7deae0a8472..714fa4bdf79478 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -1158,21 +1158,24 @@ class CodeGenDAGPatterns {
}
const CodeGenIntrinsic &getIntrinsic(const Record *R) const {
- for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i)
- if (Intrinsics[i].TheDef == R)
- return Intrinsics[i];
+ for (const CodeGenIntrinsic &I : Intrinsics.getEnabledIntrinsics())
+ if (I.TheDef == R)
+ return I;
llvm_unreachable("Unknown intrinsic!");
}
const CodeGenIntrinsic &getIntrinsicInfo(unsigned IID) const {
- if (IID - 1 < Intrinsics.size())
- return Intrinsics[IID - 1];
+ IID -= 1;
+ ArrayRef<CodeGenIntrinsic> Enabled = Intrinsics.getEnabledIntrinsics();
+ if (IID < Enabled.size())
+ return Enabled[IID];
llvm_unreachable("Bad intrinsic ID!");
}
unsigned getIntrinsicID(const Record *R) const {
- for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i)
- if (Intrinsics[i].TheDef == R)
+ ArrayRef<CodeGenIntrinsic> Enabled = Intrinsics.getEnabledIntrinsics();
+ for (unsigned i = 0, e = Enabled.size(); i != e; ++i)
+ if (Enabled[i].TheDef == R)
return i;
llvm_unreachable("Unknown intrinsic!");
}
diff --git a/llvm/utils/TableGen/IntrinsicEmitter.cpp b/llvm/utils/TableGen/IntrinsicEmitter.cpp
index 1968e7eac21e33..c1e48ffc6b0981 100644
--- a/llvm/utils/TableGen/IntrinsicEmitter.cpp
+++ b/llvm/utils/TableGen/IntrinsicEmitter.cpp
@@ -83,6 +83,9 @@ void IntrinsicEmitter::run(raw_ostream &OS, bool Enums) {
emitSourceFileHeader("Intrinsic Function Source Fragment", OS);
CodeGenIntrinsicTable Ints(Records);
+ OS << "// Enabled targets: ";
+ interleaveComma(Ints.getEnabledCommandLineTargets(), OS);
+ OS << "\n\n";
if (Enums) {
// Emit the enum information.
@@ -124,7 +127,7 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints,
// intrinsics like dbg.value.
using TargetSet = CodeGenIntrinsicTable::TargetSet;
const TargetSet *Set = nullptr;
- for (const auto &Target : Ints.getTargets()) {
+ for (const auto &Target : Ints.getAllTargets()) {
if (Target.Name == IntrinsicPrefix) {
Set = &Target;
break;
@@ -132,7 +135,7 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints,
}
if (!Set) {
// The first entry is for target independent intrinsics, so drop it.
- auto KnowTargets = Ints.getTargets().drop_front();
+ auto KnowTargets = Ints.getAllTargets().drop_front();
PrintFatalError([KnowTargets](raw_ostream &OS) {
OS << "tried to generate intrinsics for unknown target "
<< IntrinsicPrefix << "\nKnown targets are: ";
@@ -173,7 +176,10 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints,
// Emit num_intrinsics into the target neutral enum.
if (IntrinsicPrefix.empty()) {
- OS << formatv(" num_intrinsics = {}\n", Ints.size() + 1);
+ OS << formatv(" num_active_intrinsics = {},\n",
+ Ints.getEnabledIntrinsics().size() + 1);
+ OS << formatv(" num_intrinsics = {}\n",
+ Ints.getAllIntrinsics().size() + 1);
OS << "#endif\n\n";
} else {
OS << R"(}; // enum
@@ -230,7 +236,7 @@ struct IntrinsicTargetInfo {
};
static constexpr IntrinsicTargetInfo TargetInfos[] = {
)";
- for (const auto [Name, Offset, Count] : Ints.getTargets())
+ for (const auto [Name, Offset, Count] : Ints.getEnabledTargets())
OS << formatv(" {{\"{}\", {}, {}},\n", Name, Offset, Count);
OS << R"(};
#endif
@@ -244,19 +250,21 @@ void IntrinsicEmitter::EmitIntrinsicToNameTable(
#ifdef GET_INTRINSIC_NAME_TABLE
// Note that entry #0 is the invalid intrinsic!
)";
- for (const auto &Int : Ints)
+ for (const auto &Int : Ints.getEnabledIntrinsics())
OS << " \"" << Int.Name << "\",\n";
OS << "#endif\n\n";
}
void IntrinsicEmitter::EmitIntrinsicToOverloadTable(
const CodeGenIntrinsicTable &Ints, raw_ostream &OS) {
- OS << R"(// Intrinsic ID to overload bitset.
+ auto EnabledIntrinsics = Ints.getEnabledIntrinsics();
+ OS << formatv(R"(// Intrinsic ID to overload bitset.
#ifdef GET_INTRINSIC_OVERLOAD_TABLE
-static constexpr uint8_t OTable[] = {
+static constexpr uint8_t OTable[{}] = {{
0
- )";
- for (auto [I, Int] : enumerate(Ints)) {
+ )",
+ (EnabledIntrinsics.size() + 7) / 8 + 1);
+ for (auto [I, Int] : enumerate(EnabledIntrinsics)) {
// Add one to the index so we emit a null bit for the invalid #0 intrinsic.
size_t Idx = I + 1;
@@ -317,10 +325,10 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints,
std::vector<FixedEncodingTy> FixedEncodings;
SequenceToOffsetTable<TypeSigTy> LongEncodingTable;
- FixedEncodings.reserve(Ints.size());
+ FixedEncodings.reserve(Ints.getEnabledIntrinsics().size());
// Compute the unique argument type info.
- for (const CodeGenIntrinsic &Int : Ints) {
+ for (const CodeGenIntrinsic &Int : Ints.getEnabledIntrinsics()) {
// Get the signature for the intrinsic.
TypeSigTy TypeSig = ComputeTypeSignature(Int);
@@ -346,7 +354,8 @@ static constexpr {} IIT_Table[] = {{
FixedEncodingTypeName);
unsigned MaxOffset = 0;
- for (auto [Idx, FixedEncoding, Int] : enumerate(FixedEncodings, Ints)) {
+ for (auto [Idx, FixedEncoding, Int] :
+ enumerate(FixedEncodings, Ints.getEnabledIntrinsics())) {
if ((Idx & 7) == 7)
OS << "\n ";
@@ -486,7 +495,7 @@ static AttributeSet getIntrinsicArgAttributeSet(LLVMContext &C, unsigned ID) {
// Compute unique argument attribute sets.
std::map<SmallVector<CodeGenIntrinsic::ArgAttribute, 0>, unsigned>
UniqArgAttributes;
- for (const CodeGenIntrinsic &Int : Ints) {
+ for (const CodeGenIntrinsic &Int : Ints.getEnabledIntrinsics()) {
for (auto &Attrs : Int.ArgumentAttributes) {
if (Attrs.empty())
continue;
@@ -527,7 +536,7 @@ static AttributeSet getIntrinsicFnAttributeSet(LLVMContext &C, unsigned ID) {
switch (ID) {
default: llvm_unreachable("Invalid attribute set number");)";
- for (const CodeGenIntrinsic &Int : Ints) {
+ for (const CodeGenIntrinsic &Int : Ints.getEnabledIntrinsics()) {
if (!hasFnAttributes(Int))
continue;
unsigned ID = UniqFnAttributes.size();
@@ -587,7 +596,7 @@ AttributeList Intrinsic::getAttributes(LLVMContext &C, ID id) {
// arguments or not.
std::map<const CodeGenIntrinsic *, unsigned, AttributeComparator>
UniqAttributes;
- for (const CodeGenIntrinsic &Int : Ints) {
+ for (const CodeGenIntrinsic &Int : Ints.getEnabledIntrinsics()) {
unsigned ID = UniqAttributes.size();
UniqAttributes.try_emplace(&Int, ID);
}
@@ -603,7 +612,7 @@ AttributeList Intrinsic::getAttributes(LLVMContext &C, ID id) {
// Emit an array of AttributeList. Most intrinsics will have at least one
// entry, for the function itself (index ~1), which is usually nounwind.
OS << " static constexpr uint16_t IntrinsicsToAttributesMap[] = {";
- for (const CodeGenIntrinsic &Int : Ints) {
+ for (const CodeGenIntrinsic &Int : Ints.getEnabledIntrinsics()) {
uint16_t FnAttrIndex = hasFnAttributes(Int) ? UniqFnAttributes[&Int] : 0;
OS << formatv("\n {} << 8 | {}, // {}", FnAttrIndex,
UniqAttributes[&Int], Int.Name);
@@ -677,7 +686,7 @@ void IntrinsicEmitter::EmitIntrinsicToBuiltinMap(
std::pair<std::map<StringRef, StringRef>, std::optional<StringRef>>;
std::map<StringRef, BIMEntryTy> BuiltinMap;
- for (const CodeGenIntrinsic &Int : Ints) {
+ for (const CodeGenIntrinsic &Int : Ints.getEnabledIntrinsics()) {
StringRef BuiltinName = IsClang ? Int.ClangBuiltinName : Int.MSBuiltinName;
if (BuiltinName.empty())
continue;
@@ -728,7 +737,7 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix,
if (BuiltinMap.empty()) {
OS << formatv(R"(
return not_intrinsic;
- }
+}
#endif // GET_LLVM_INTRINSIC_FOR_{}_BUILTIN
)",
UpperCompilerName);
@@ -753,11 +762,13 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix,
// Emit a per target table of bultin names.
bool HasTargetIndependentBuiltins = false;
+ bool HasTargetDependentBuiltins = false;
StringRef TargetIndepndentCommonPrefix;
for (const auto &[TargetPrefix, Entry] : BuiltinMap) {
const auto &[Map, CommonPrefix] = Entry;
if (!TargetPrefix.empty()) {
OS << formatv(" // Builtins for {0}.\n", TargetPrefix);
+ HasTargetDependentBuiltins = true;
} else {
OS << " // Target independent builtins.\n";
HasTargetIndependentBuiltins = true;
@@ -775,30 +786,32 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix,
OS << formatv(" }; // {}Names\n\n", TargetPrefix);
}
- // After emitting the builtin tables for all targets, emit a lookup table for
- // all targets. We will use binary search, similar to the table for builtin
- // names to lookup into this table.
- OS << R"(
- struct TargetEntry {
- StringLiteral TargetPrefix;
- ArrayRef<BuiltinEntry> Names;
- StringLiteral CommonPrefix;
- bool operator<(StringRef RHS) const {
- return TargetPrefix < RHS;
+ if (HasTargetDependentBuiltins) {
+ // After emitting the builtin tables for all targets, emit a lookup table
+ // for all targets. We will use binary search, similar to the table for
+ // builtin names to lookup into this table.
+ OS << R"(
+ struct TargetEntry {
+ StringLiteral TargetPrefix;
+ ArrayRef<BuiltinEntry> Names;
+ StringLiteral CommonPrefix;
+ bool operator<(StringRef RHS) const {
+ return TargetPrefix < RHS;
+ };
};
- };
- static constexpr TargetEntry TargetTable[] = {
-)";
+ static constexpr TargetEntry TargetTable[] = {
+ )";
- for (const auto &[TargetPrefix, Entry] : BuiltinMap) {
- const auto &[Map, CommonPrefix] = Entry;
- if (TargetPrefix.empty())
- continue;
- OS << formatv(R"( {{"{0}", {0}Names, "{1}"},)", TargetPrefix,
- CommonPrefix)
- << "\n";
+ for (const auto &[TargetPrefix, Entry] : BuiltinMap) {
+ const auto &[Map, CommonPrefix] = Entry;
+ if (TargetPrefix.empty())
+ continue;
+ OS << formatv(R"( {{"{0}", {0}Names, "{1}"},)", TargetPrefix,
+ CommonPrefix)
+ << "\n";
+ }
+ OS << " };\n";
}
- OS << " };\n";
// Now for the actual lookup, first check the target independent table if
// we emitted one.
@@ -817,8 +830,10 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix,
TargetIndepndentCommonPrefix);
}
- // If a target independent builtin was not found, lookup the target specific.
- OS << formatv(R"(
+ if (HasTargetDependentBuiltins) {
+ // If a target independent builtin was not found, lookup the target
+ // specific.
+ OS << R"(
auto TI = lower_bound(TargetTable, TargetPrefix);
if (TI == std::end(TargetTable) || TI->TargetPrefix != TargetPrefix)
return not_intrinsic;
@@ -830,6 +845,12 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix,
if (II == std::end(TI->Names) || II->getName() != BuiltinName)
return not_intrinsic;
return II->IntrinsicID;
+)";
+ } else {
+ OS << " return not_intrinsic;";
+ }
+
+ OS << formatv(R"(
}
#endif // GET_LLVM_INTRINSIC_FOR_{}_BUILTIN
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