[llvm] [AMDGPU] Implement hasBitTest to Optimize Bit Testing Operations (PR #112652)

[Harrison Hao via llvm-commits]

https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/112652

>From 0354045aeacb1ddbeffe6f57ec2ec2937033b143 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 17 Oct 2024 11:25:11 +0800
Subject: [PATCH 1/2] [AMDGPU] Implement hasBitTest to Optimize Bit Testing
 Operations

---
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 21 +++++++++++++++++++
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h   |  2 ++
 2 files changed, 23 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 0f65df0763cc83..0f90fc1dfa750a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -6043,3 +6043,24 @@ bool AMDGPUTargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,
                                                Register N0, Register N1) const {
   return MRI.hasOneNonDBGUse(N0); // FIXME: handle regbanks
 }
+
+bool AMDGPUTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
+  if (X->isDivergent() || Y->isDivergent())
+    return false;
+
+  EVT VT = X.getValueType();
+
+  if (VT != MVT::i32 && VT != MVT::i64)
+    return false;
+
+  auto *ConstantMaskNode = dyn_cast<ConstantSDNode>(Y);
+  if (!ConstantMaskNode)
+    return false;
+
+  APInt MaskValue = ConstantMaskNode->getAPIntValue();
+
+  if (!MaskValue.isPowerOf2())
+    return false;
+
+  return true;
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index b2fd31cb2346eb..73240bea4175a9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -387,6 +387,8 @@ class AMDGPUTargetLowering : public TargetLowering {
   MVT getFenceOperandTy(const DataLayout &DL) const override {
     return MVT::i32;
   }
+
+  bool hasBitTest(SDValue X, SDValue Y) const override;
 };
 
 namespace AMDGPUISD {

>From fc9869a0986bb0ccbd843cc5a0dbc4c5691efec0 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Fri, 18 Oct 2024 18:55:18 +0800
Subject: [PATCH 2/2] [AMDGPU] Move to SIISelLowering.

---
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 21 ----------------
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h   |  2 --
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp     | 25 +++++++++++++++++++
 llvm/lib/Target/AMDGPU/SIISelLowering.h       |  1 +
 4 files changed, 26 insertions(+), 23 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 0f90fc1dfa750a..0f65df0763cc83 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -6043,24 +6043,3 @@ bool AMDGPUTargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,
                                                Register N0, Register N1) const {
   return MRI.hasOneNonDBGUse(N0); // FIXME: handle regbanks
 }
-
-bool AMDGPUTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
-  if (X->isDivergent() || Y->isDivergent())
-    return false;
-
-  EVT VT = X.getValueType();
-
-  if (VT != MVT::i32 && VT != MVT::i64)
-    return false;
-
-  auto *ConstantMaskNode = dyn_cast<ConstantSDNode>(Y);
-  if (!ConstantMaskNode)
-    return false;
-
-  APInt MaskValue = ConstantMaskNode->getAPIntValue();
-
-  if (!MaskValue.isPowerOf2())
-    return false;
-
-  return true;
-}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 73240bea4175a9..b2fd31cb2346eb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -387,8 +387,6 @@ class AMDGPUTargetLowering : public TargetLowering {
   MVT getFenceOperandTy(const DataLayout &DL) const override {
     return MVT::i32;
   }
-
-  bool hasBitTest(SDValue X, SDValue Y) const override;
 };
 
 namespace AMDGPUISD {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index de9173e923ab5c..c2f6b6fec3a2e7 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -16890,3 +16890,28 @@ SITargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
   AI->eraseFromParent();
   return LI;
 }
+
+bool SITargetLowering::hasBitTest(SDValue X, SDValue Y) const {
+  if (X->isDivergent() || Y->isDivergent())
+    return false;
+
+  EVT VT = X.getValueType();
+
+  if (VT != MVT::i32 && VT != MVT::i64)
+    return false;
+
+  if (VT.isVector()) {
+    EVT ScalarType = VT.getScalarType();
+    if (ScalarType != MVT::i32 && ScalarType != MVT::i64)
+      return false;
+  }
+
+  auto *IsConstOrIsConstSplat = dyn_cast<ConstantSDNode>(Y);
+  if (!dyn_cast<ConstantSDNode>(Y))
+    return false;
+
+  if (!IsConstOrIsConstSplat->getAPIntValue().isPowerOf2())
+    return false;
+
+  return true;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index 6c3edf37945e24..3b4caa2336aec6 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -598,6 +598,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
 
   MachineMemOperand::Flags
   getTargetMMOFlags(const Instruction &I) const override;
+  bool hasBitTest(SDValue X, SDValue Y) const override;
 };
 
 // Returns true if argument is a boolean value which is not serialized into