[llvm] clastb representation in existing IR, and AArch64 codegen (PR #112738)

[via llvm-commits]

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git-clang-format --diff 85c17e40926132575d1b98ca1a36b8394fe511cd b80e292d1e08b63abdadd645431649c1912c293e --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ccd89af6eb..b6b139c396 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -19535,7 +19535,10 @@ performLastActiveExtractEltCombine(SDNode *N,
   if (Size.getOpcode() != ISD::VSCALE)
     return SDValue();
 
-  unsigned NElts = N->getOperand(0)->getValueType(0).getVectorElementCount().getKnownMinValue();
+  unsigned NElts = N->getOperand(0)
+                       ->getValueType(0)
+                       .getVectorElementCount()
+                       .getKnownMinValue();
   if (Size.getConstantOperandVal(0) != NElts)
     return SDValue();
 
@@ -24456,8 +24459,8 @@ static SDValue foldCSELOfLASTB(SDNode *N, SelectionDAG &DAG) {
   if (CC != AArch64CC::NE)
     return SDValue();
 
-  return DAG.getNode(AArch64ISD::CLASTB_N, SDLoc(N), N->getValueType(0),
-                     LBPred, Op1, Op0.getOperand(1));
+  return DAG.getNode(AArch64ISD::CLASTB_N, SDLoc(N), N->getValueType(0), LBPred,
+                     Op1, Op0.getOperand(1));
 }
 
 // Optimize CSEL instructions

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https://github.com/llvm/llvm-project/pull/112738