[llvm] [AMDGPU] Implement hasBitTest to Optimize Bit Testing Operations (PR #112652)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 16 20:31:19 PDT 2024
https://github.com/harrisonGPU created https://github.com/llvm/llvm-project/pull/112652
>From https://github.com/llvm/llvm-project/issues/112550
This PR implements the `hasBitTest` function for AMDGPU in the `TargetLowering` class, enabling LLVM to effectively recognize and optimize bit test operations for scalar 32-bit and 64-bit integer types (`i32` and `i64`).
For example:
```bash
%mask = i32 16 ; Binary: 0b00010000, tests the 5th bit
%test = and i32 %X, %mask
%cmp = icmp eq i32 %test, 0
br i1 %cmp, label %if_zero, label %if_nonzero
if_zero:
; Execute action if the 5th bit in %X is 0
...
if_nonzero:
; Execute alternative action if the 5th bit in %X is not 0
...
```
This use of `hasBitTest` ensures direct application of `S_BITCMP0_B32`, streamlining the generation of machine code for bit testing in AMDGPU targets.
>From 0354045aeacb1ddbeffe6f57ec2ec2937033b143 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 17 Oct 2024 11:25:11 +0800
Subject: [PATCH] [AMDGPU] Implement hasBitTest to Optimize Bit Testing
Operations
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 21 +++++++++++++++++++
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 0f65df0763cc83..0f90fc1dfa750a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -6043,3 +6043,24 @@ bool AMDGPUTargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,
Register N0, Register N1) const {
return MRI.hasOneNonDBGUse(N0); // FIXME: handle regbanks
}
+
+bool AMDGPUTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
+ if (X->isDivergent() || Y->isDivergent())
+ return false;
+
+ EVT VT = X.getValueType();
+
+ if (VT != MVT::i32 && VT != MVT::i64)
+ return false;
+
+ auto *ConstantMaskNode = dyn_cast<ConstantSDNode>(Y);
+ if (!ConstantMaskNode)
+ return false;
+
+ APInt MaskValue = ConstantMaskNode->getAPIntValue();
+
+ if (!MaskValue.isPowerOf2())
+ return false;
+
+ return true;
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index b2fd31cb2346eb..73240bea4175a9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -387,6 +387,8 @@ class AMDGPUTargetLowering : public TargetLowering {
MVT getFenceOperandTy(const DataLayout &DL) const override {
return MVT::i32;
}
+
+ bool hasBitTest(SDValue X, SDValue Y) const override;
};
namespace AMDGPUISD {
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