[llvm] [PowerPC] Expand global named register support (PR #112603)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 16 12:46:38 PDT 2024
https://github.com/lei137 created https://github.com/llvm/llvm-project/pull/112603
Enable all valid registers for intrinsics that read from and write
to global named registers.
>From 06987ed6375fb81d03647bf8c9fd638ca182acad Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 8 Oct 2024 13:52:15 -0400
Subject: [PATCH 1/4] [PowerPC] Expand global named register support
Enable all valid registers for intrinsics that read from and write
to global named registers.
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index cec1e507f08f2f..ec0f00ecb0eb67 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -17319,8 +17319,9 @@ SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
return FrameAddr;
}
-// FIXME? Maybe this could be a TableGen attribute on some registers and
-// this table could be generated automatically from RegInfo.
+#define GET_REGISTER_MATCHER
+#include "PPCGenAsmMatcher.inc"
+
Register PPCTargetLowering::getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const {
bool isPPC64 = Subtarget.isPPC64();
@@ -17329,15 +17330,15 @@ Register PPCTargetLowering::getRegisterByName(const char* RegName, LLT VT,
if (!is64Bit && VT != LLT::scalar(32))
report_fatal_error("Invalid register global variable type");
- Register Reg = StringSwitch<Register>(RegName)
- .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
- .Case("r2", isPPC64 ? Register() : PPC::R2)
- .Case("r13", (is64Bit ? PPC::X13 : PPC::R13))
- .Default(Register());
+ Register Reg = MatchRegisterName(RegName);
+ if (!Reg)
+ report_fatal_error(Twine("Invalid global name register \""
+ + StringRef(RegName) + "\"."));
- if (Reg)
- return Reg;
- report_fatal_error("Invalid register name global variable");
+ if (!Subtarget.getRegisterInfo()->getReservedRegs(MF).test(Reg))
+ report_fatal_error(Twine("Trying to obtain non-reservable register \"" +
+ StringRef(RegName) + "\"."));
+ return Reg;
}
bool PPCTargetLowering::isAccessedAsGotIndirect(SDValue GA) const {
>From 770c90c53d4d349855a6b1d726f23dbd16864dc2 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Thu, 10 Oct 2024 17:51:56 -0400
Subject: [PATCH 2/4] update tc err message
---
llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll | 9 ++++-----
llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll | 3 +--
llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll | 3 +--
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll
index 11cb72296e2c43..be2fae8f3458be 100644
--- a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll
+++ b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll
@@ -1,11 +1,10 @@
-; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
-; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
-; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: not --crash llc -O0 < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: not --crash llc -O0 < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: not --crash llc -O0 < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
define i32 @get_reg() nounwind {
entry:
-; FIXME: Include an allocatable-specific error message
-; CHECK: Invalid register name global variable
+; CHECK: Trying to obtain non-reservable register "r0".
%reg = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %reg
}
diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll
index 3df778f445c733..b245c7d6f76c12 100644
--- a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll
+++ b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll
@@ -3,8 +3,7 @@
define i64 @get_reg() nounwind {
entry:
-; FIXME: Include an allocatable-specific error message
-; CHECK: Invalid register name global variable
+; CHECK: Trying to obtain non-reservable register "r2".
%reg = call i64 @llvm.read_register.i64(metadata !0)
ret i64 %reg
}
diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll
index ca79f857548ebe..ac79aa381ea7e0 100644
--- a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll
+++ b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll
@@ -3,8 +3,7 @@
define i32 @get_reg() nounwind {
entry:
-; FIXME: Include an allocatable-specific error message
-; CHECK-NOTPPC32: Invalid register name global variable
+; CHECK-NOTPPC32: Trying to obtain non-reservable register "r2".
%reg = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %reg
>From fe6068509ccd0d8f8bb4bc289efef8545be43651 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Wed, 16 Oct 2024 14:01:54 -0400
Subject: [PATCH 3/4] fix regId for 64bit
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index ec0f00ecb0eb67..3a348d124760be 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -17324,10 +17324,9 @@ SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
Register PPCTargetLowering::getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const {
- bool isPPC64 = Subtarget.isPPC64();
- bool is64Bit = isPPC64 && VT == LLT::scalar(64);
- if (!is64Bit && VT != LLT::scalar(32))
+ bool Is64Bit = Subtarget.isPPC64() && VT == LLT::scalar(64);
+ if (!Is64Bit && VT != LLT::scalar(32))
report_fatal_error("Invalid register global variable type");
Register Reg = MatchRegisterName(RegName);
@@ -17335,7 +17334,11 @@ Register PPCTargetLowering::getRegisterByName(const char* RegName, LLT VT,
report_fatal_error(Twine("Invalid global name register \""
+ StringRef(RegName) + "\"."));
- if (!Subtarget.getRegisterInfo()->getReservedRegs(MF).test(Reg))
+ // Convert GPR to GP8R register for 64bit.
+ if (Is64Bit && StringRef(RegName).starts_with_insensitive("r"))
+ Reg = Reg.id() - PPC::R0 + PPC::X0;
+
+ if (Subtarget.getRegisterInfo()->getReservedRegs(MF).test(Reg))
report_fatal_error(Twine("Trying to obtain non-reservable register \"" +
StringRef(RegName) + "\"."));
return Reg;
>From 7907275d8dd3476d8d5beb01d875745b670d1977 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Wed, 16 Oct 2024 15:43:31 -0400
Subject: [PATCH 4/4] do not allow usage of reserved registers
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 3a348d124760be..98b0a5ad4db0ee 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -17338,7 +17338,7 @@ Register PPCTargetLowering::getRegisterByName(const char* RegName, LLT VT,
if (Is64Bit && StringRef(RegName).starts_with_insensitive("r"))
Reg = Reg.id() - PPC::R0 + PPC::X0;
- if (Subtarget.getRegisterInfo()->getReservedRegs(MF).test(Reg))
+ if (!Subtarget.getRegisterInfo()->getReservedRegs(MF).test(Reg))
report_fatal_error(Twine("Trying to obtain non-reservable register \"" +
StringRef(RegName) + "\"."));
return Reg;
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