[llvm] [AArch64][SVE] Avoid transfer to GPRs for fp -> int -> fp conversions (PR #112564)

[Sander de Smalen via llvm-commits]

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@@ -2421,6 +2421,42 @@ let Predicates = [HasSVEorSME] in {
   defm FSQRT_ZPmZ  : sve_fp_2op_p_zd_HSD<0b01101, "fsqrt",  AArch64fsqrt_mt>;
 } // End HasSVEorSME
 
+// Helper for creating scalar fp -> int -> fp conversions using SVE.
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sdesmalen-arm wrote:

Rather than doing this in TableGen patterns, I was hoping that we could emulate the `FP_TO_INT` and `INT_TO_FP` with SVE instructions by using Custom lowering in AArch64ISelLowering, so that these operations are lowered using `LowerFixedLengthIntToFPToSVE` and `LowerFixedLengthFPToIntToSVE`. I would then expect a DAGCombine to fold away the scalar extracts/inserts, so that we'd end up with the same codegen as you get here, but without the need to explicitly pattern-match `FP_TO_INT(INT_TO_FP(..))`.

https://github.com/llvm/llvm-project/pull/112564