[llvm] [LLVM][IR] Use splat syntax when printing ConstantDataVector. (PR #112548)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 16 07:06:02 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: Paul Walker (paulwalker-arm)
<details>
<summary>Changes</summary>
Whilst this PR is not finished (there are many tests that still need updating) I'm sending for review because there's no value in me continuing if the goal of the PR is not acceptable. Likewise, if there's a better way to navigate the transition then I'm all ears.
I'm thinking that sooner or later the pain of having to update the tests will be required so I figured it was worth getting in early as an NFC patch rather than attempting this when trying to make the vector ConstantInt/ConstantFP support enabled by default. Doing this early will also make it easier to track the cases where code quality diverges so I can circle back to them once the functional issues have been resolved..
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Patch is 6.56 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/112548.diff
830 Files Affected:
- (modified) llvm/lib/IR/AsmWriter.cpp (+45)
- (modified) llvm/lib/IR/Constants.cpp (+4-2)
- (modified) llvm/test/Analysis/CostModel/AArch64/arith-fp.ll (+7-7)
- (modified) llvm/test/Analysis/CostModel/AArch64/arith-widening.ll (+3-3)
- (modified) llvm/test/Analysis/CostModel/AArch64/div.ll (+72-72)
- (modified) llvm/test/Analysis/CostModel/AArch64/div_cte.ll (+6-6)
- (modified) llvm/test/Analysis/CostModel/AArch64/fshl.ll (+4-4)
- (modified) llvm/test/Analysis/CostModel/AArch64/fshr.ll (+4-4)
- (modified) llvm/test/Analysis/CostModel/AArch64/rem.ll (+72-72)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/div.ll (+216-216)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll (+192-192)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/fneg.ll (+12-12)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/mul.ll (+96-96)
- (modified) llvm/test/Analysis/CostModel/AMDGPU/rem.ll (+216-216)
- (modified) llvm/test/Analysis/CostModel/ARM/divrem.ll (+410-410)
- (modified) llvm/test/Analysis/CostModel/RISCV/arith-int.ll (+6-6)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll (+6-6)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-phi-const.ll (+14-14)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-select.ll (+1-1)
- (modified) llvm/test/Analysis/CostModel/X86/arith-fp-codesize.ll (+24-24)
- (modified) llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll (+48-48)
- (modified) llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll (+42-42)
- (modified) llvm/test/Analysis/CostModel/X86/arith-fp.ll (+48-48)
- (modified) llvm/test/Analysis/CostModel/X86/div-codesize.ll (+168-168)
- (modified) llvm/test/Analysis/CostModel/X86/div-latency.ll (+192-192)
- (modified) llvm/test/Analysis/CostModel/X86/div-sizelatency.ll (+168-168)
- (modified) llvm/test/Analysis/CostModel/X86/div.ll (+384-384)
- (modified) llvm/test/Analysis/CostModel/X86/fshl-codesize.ll (+252-252)
- (modified) llvm/test/Analysis/CostModel/X86/fshl-latency.ll (+243-243)
- (modified) llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll (+276-276)
- (modified) llvm/test/Analysis/CostModel/X86/fshl.ll (+243-243)
- (modified) llvm/test/Analysis/CostModel/X86/fshr-codesize.ll (+252-252)
- (modified) llvm/test/Analysis/CostModel/X86/fshr-latency.ll (+243-243)
- (modified) llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll (+276-276)
- (modified) llvm/test/Analysis/CostModel/X86/fshr.ll (+243-243)
- (modified) llvm/test/Analysis/CostModel/X86/mul-codesize.ll (+192-192)
- (modified) llvm/test/Analysis/CostModel/X86/mul-latency.ll (+192-192)
- (modified) llvm/test/Analysis/CostModel/X86/mul-sizelatency.ll (+192-192)
- (modified) llvm/test/Analysis/CostModel/X86/mul.ll (+192-192)
- (modified) llvm/test/Analysis/CostModel/X86/rem-codesize.ll (+180-180)
- (modified) llvm/test/Analysis/CostModel/X86/rem-latency.ll (+168-168)
- (modified) llvm/test/Analysis/CostModel/X86/rem-sizelatency.ll (+168-168)
- (modified) llvm/test/Analysis/CostModel/X86/rem.ll (+384-384)
- (modified) llvm/test/Analysis/CostModel/X86/slm-arith-costs.ll (+4-4)
- (modified) llvm/test/Analysis/CostModel/X86/vdiv-cost.ll (+21-21)
- (modified) llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll (+77-77)
- (modified) llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll (+80-80)
- (modified) llvm/test/Analysis/CostModel/X86/vshift-ashr-cost.ll (+80-80)
- (modified) llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll (+92-92)
- (modified) llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll (+79-79)
- (modified) llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll (+75-75)
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- (modified) llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll (+82-82)
- (modified) llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll (+75-75)
- (modified) llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll (+75-75)
- (modified) llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll ()
- (modified) llvm/test/Analysis/CostModel/X86/vshift-shl-cost.ll ()
- (modified) llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll ()
- (modified) llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll ()
- (modified) llvm/test/Analysis/ValueTracking/known-non-zero.ll (+3-3)
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- (modified) llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll (+4-4)
- (modified) llvm/test/Analysis/ValueTracking/knownzero-shift.ll (+2-2)
- (modified) llvm/test/Analysis/ValueTracking/numsignbits-shl.ll (+6-6)
- (modified) llvm/test/Assembler/ConstantExprFold.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll (+9-9)
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- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-mul24.ll (+22-22)
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- (modified) llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll (+3-3)
- (modified) llvm/test/CodeGen/Hexagon/autohvx/vector-align-tbaa.ll (+9-9)
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- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll (+11-11)
- (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-const.ll (+161-25)
- (modified) llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll (+16-16)
- (modified) llvm/test/CodeGen/X86/codegen-prepare-extload.ll (+1-1)
- (modified) llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll (+689-689)
- (modified) llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll (+121-121)
- (modified) llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll (+37-37)
- (modified) llvm/test/Instrumentation/MemorySanitizer/X86/avx2-intrinsics-x86.ll (+39-39)
- (modified) llvm/test/Instrumentation/MemorySanitizer/X86/sse2-intrinsics-x86.ll (+51-51)
- (modified) llvm/test/Instrumentation/MemorySanitizer/X86/sse41-intrinsics-x86.ll (+14-14)
- (modified) llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll (+18-18)
- (modified) llvm/test/Instrumentation/MemorySanitizer/vector-track-origins-neon.ll (-2)
- (modified) llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll (+6-6)
- (modified) llvm/test/Transforms/AggressiveInstCombine/ARM/fptosisat.ll (+10-10)
- (modified) llvm/test/Transforms/AggressiveInstCombine/X86/fptosisat.ll (+2-2)
- (modified) llvm/test/Transforms/AggressiveInstCombine/masked-cmp.ll (+5-5)
- (modified) llvm/test/Transforms/AggressiveInstCombine/popcount.ll (+15-15)
- (modified) llvm/test/Transforms/AggressiveInstCombine/trunc_multi_uses.ll (+4-4)
- (modified) llvm/test/Transforms/AggressiveInstCombine/vector-or-load.ll (+1-1)
- (modified) llvm/test/Transforms/Attributor/nofpclass-powi.ll (+2-2)
- (modified) llvm/test/Transforms/Attributor/nofpclass.ll (+4-4)
- (modified) llvm/test/Transforms/Attributor/value-simplify-pointer-info-vec.ll (+2-2)
- (modified) llvm/test/Transforms/BDCE/binops-multiuse.ll (+2-2)
- (modified) llvm/test/Transforms/BDCE/dead-uses.ll (+4-4)
- (modified) llvm/test/Transforms/BDCE/vectors-inseltpoison.ll (+15-15)
- (modified) llvm/test/Transforms/BDCE/vectors.ll (+15-15)
- (modified) llvm/test/Transforms/CodeGenPrepare/X86/fold-loop-of-urem.ll (+7-7)
- (modified) llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll (+5-11)
- (modified) llvm/test/Transforms/ConstraintElimination/vector-compares.ll (+1-1)
- (modified) llvm/test/Transforms/CorrelatedValuePropagation/icmp.ll (+2-2)
- (modified) llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll (+2-2)
- (modified) llvm/test/Transforms/CorrelatedValuePropagation/vectors.ll (+11-11)
- (modified) llvm/test/Transforms/DeadStoreElimination/X86/gather-null-pointer.ll (+3-3)
- (modified) llvm/test/Transforms/DeadStoreElimination/offsetted-overlapping-stores.ll (+1-1)
- (modified) llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll (+2-2)
- (modified) llvm/test/Transforms/EarlyCSE/commute.ll (+4-4)
- (modified) llvm/test/Transforms/EarlyCSE/gep.ll (+1-1)
- (modified) llvm/test/Transforms/GVN/non-integral-pointers-inseltpoison.ll (+2-2)
- (modified) llvm/test/Transforms/GVN/non-integral-pointers.ll (+1-1)
- (modified) llvm/test/Transforms/InferAddressSpaces/AMDGPU/infer-getelementptr.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/2007-03-21-SignedRangeTest.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/2008-01-21-MulTrunc.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/2008-12-17-SRemNegConstVec.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/X86/x86-masked-memops.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/X86/x86-movmsk.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/X86/x86-muldq-inseltpoison.ll (+16-16)
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- (modified) llvm/test/Transforms/InstCombine/ashr-demand.ll (+4-4)
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- (modified) llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/fold-bin-operand.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/fold-select-fmul-if-zero.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/fold-select-trunc.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/fold-signbit-test-power2.ll (+8-8)
- (modified) llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll (+3-3)
- (modified) llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/fsh.ll (+3-3)
- (modified) llvm/test/Transforms/InstCombine/funnel.ll (+5-5)
- (modified) llvm/test/Transforms/InstCombine/gep-combine-loop-invariant.ll (+5-5)
- (modified) llvm/test/Transforms/InstCombine/gep-custom-dl.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/gep-vector.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/get-lowbitmask-upto-and-including-bit.ll (+8-8)
- (modified) llvm/test/Transforms/InstCombine/getelementptr.ll (+3-3)
- (modified) llvm/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/high-bit-signmask.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/hoist-negation-out-of-bias-calculation-with-constant.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/hoist-negation-out-of-bias-calculation.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/hoist-not-from-ashr-operand.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/icmp-add.ll (+17-17)
- (modified) llvm/test/Transforms/InstCombine/icmp-and-shift.ll (+13-13)
- (modified) llvm/test/Transforms/InstCombine/icmp-div-constant.ll (+5-5)
- (modified) llvm/test/Transforms/InstCombine/icmp-logical.ll (+12-12)
- (modified) llvm/test/Transforms/InstCombine/icmp-mul-and.ll (+3-3)
- (modified) llvm/test/Transforms/InstCombine/icmp-mul.ll (+9-9)
- (modified) llvm/test/Transforms/InstCombine/icmp-of-and-x.ll (+2-2)
``````````diff
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
index 6adb8d6a742255..93c66ee6d14540 100644
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -89,6 +89,11 @@
using namespace llvm;
+namespace llvm {
+extern cl::opt<bool> UseConstantIntForFixedLengthSplat;
+extern cl::opt<bool> UseConstantFPForFixedLengthSplat;
+} // namespace llvm
+
// Make virtual table appear in this compilation unit.
AssemblyAnnotationWriter::~AssemblyAnnotationWriter() = default;
@@ -1687,6 +1692,46 @@ static void WriteConstantInternal(raw_ostream &Out, const Constant *CV,
return;
}
+ // When in the mode where Constant{Int,FP} do not support vector types the
+ // "splat(Ty val)" syntax is interpreted as a ConstantDataVector. Maintaining
+ // this association when outputiing the IR will significantly reduce the
+ // output changes when in the mode where Constant{Int,FP} do support vector
+ // types. In turn this should make it easier to spot difference in output
+ // when switching between the modes. Once the transition is complete this
+ // code will be removed.
+ if (const ConstantDataVector *CDV = dyn_cast<ConstantDataVector>(CV)) {
+ if (auto *SplatVal = CDV->getSplatValue()) {
+ Type* EltTy = SplatVal->getType();
+
+ if (EltTy->isIntegerTy() && !UseConstantIntForFixedLengthSplat) {
+ if (const ConstantInt *CI = dyn_cast<ConstantInt>(SplatVal)) {
+ Out << "splat (";
+ WriterCtx.TypePrinter->print(EltTy, Out);
+ Out << " ";
+
+ if (EltTy->isIntegerTy(1))
+ Out << (CI->getZExtValue() ? "true" : "false");
+ else
+ Out << CI->getValue();
+
+ Out << ")";
+ return;
+ }
+ }
+
+ if (EltTy->isFloatingPointTy() && !UseConstantFPForFixedLengthSplat) {
+ if (const ConstantFP *CFP = dyn_cast<ConstantFP>(SplatVal)) {
+ Out << "splat (";
+ WriterCtx.TypePrinter->print(EltTy, Out);
+ Out << " ";
+ WriteAPFloatInternal(Out, CFP->getValueAPF());
+ Out << ")";
+ return;
+ }
+ }
+ }
+ }
+
if (isa<ConstantVector>(CV) || isa<ConstantDataVector>(CV)) {
auto *CVVTy = cast<FixedVectorType>(CV->getType());
Type *ETy = CVVTy->getElementType();
diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp
index fe3a086c5772de..d716b5c900d8e4 100644
--- a/llvm/lib/IR/Constants.cpp
+++ b/llvm/lib/IR/Constants.cpp
@@ -36,12 +36,14 @@ using namespace llvm;
using namespace PatternMatch;
// As set of temporary options to help migrate how splats are represented.
-static cl::opt<bool> UseConstantIntForFixedLengthSplat(
+namespace llvm {
+cl::opt<bool> UseConstantIntForFixedLengthSplat(
"use-constant-int-for-fixed-length-splat", cl::init(false), cl::Hidden,
cl::desc("Use ConstantInt's native fixed-length vector splat support."));
-static cl::opt<bool> UseConstantFPForFixedLengthSplat(
+cl::opt<bool> UseConstantFPForFixedLengthSplat(
"use-constant-fp-for-fixed-length-splat", cl::init(false), cl::Hidden,
cl::desc("Use ConstantFP's native fixed-length vector splat support."));
+}
static cl::opt<bool> UseConstantIntForScalableSplat(
"use-constant-int-for-scalable-splat", cl::init(false), cl::Hidden,
cl::desc("Use ConstantInt's native scalable vector splat support."));
diff --git a/llvm/test/Analysis/CostModel/AArch64/arith-fp.ll b/llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
index aaffd97b92b2de..b329a5607acb97 100644
--- a/llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
@@ -70,15 +70,15 @@ define i32 @fsub(i32 %arg) {
define i32 @fneg_idiom(i32 %arg) {
; CHECK-LABEL: 'fneg_idiom'
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F16 = fsub half 0xH8000, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F16 = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F16 = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F16 = fsub <4 x half> splat (half 0xH8000), undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F16 = fsub <8 x half> splat (half 0xH8000), undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F32 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F32 = fsub <2 x float> splat (float -0.000000e+00), undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> splat (float -0.000000e+00), undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> splat (float -0.000000e+00), undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double -0.000000e+00, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> splat (double -0.000000e+00), undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> splat (double -0.000000e+00), undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%F16 = fsub half -0.0, undef
diff --git a/llvm/test/Analysis/CostModel/AArch64/arith-widening.ll b/llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
index 52f6f73525a3b9..303bcfa289577c 100644
--- a/llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
@@ -2091,11 +2091,11 @@ define void @extmulv16(<16 x i8> %i8, <16 x i16> %i16, <16 x i32> %i32, <16 x i6
define void @extmul_const(<8 x i8> %i8, <8 x i16> %i16, <8 x i32> %i32, <8 x i64> %i64) {
; CHECK-LABEL: 'extmul_const'
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sl1_8_16 = sext <8 x i8> %i8 to <8 x i16>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %asl_8_16 = mul <8 x i16> %sl1_8_16, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %asl_8_16 = mul <8 x i16> %sl1_8_16, splat (i16 10)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %zl1_8_16 = zext <8 x i8> %i8 to <8 x i16>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %azl_8_16 = mul <8 x i16> %zl1_8_16, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %azl_8_16 = mul <8 x i16> %zl1_8_16, splat (i16 10)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %zl1_8_16b = zext <8 x i8> %i8 to <8 x i16>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and = and <8 x i16> %sl1_8_16, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %and = and <8 x i16> %sl1_8_16, splat (i16 255)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %aal_8_16 = mul <8 x i16> %zl1_8_16b, %and
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
diff --git a/llvm/test/Analysis/CostModel/AArch64/div.ll b/llvm/test/Analysis/CostModel/AArch64/div.ll
index 2ceaf0c6f536af..ada0be66c27b5a 100644
--- a/llvm/test/Analysis/CostModel/AArch64/div.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/div.ll
@@ -192,21 +192,21 @@ define i32 @sdiv_uniformconst() {
; CHECK-LABEL: 'sdiv_uniformconst'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I128 = sdiv i128 undef, 7
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I64 = sdiv i64 undef, 7
-; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2i64 = sdiv <2 x i64> undef, <i64 7, i64 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4i64 = sdiv <4 x i64> undef, <i64 7, i64 7, i64 7, i64 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i64 = sdiv <8 x i64> undef, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2i64 = sdiv <2 x i64> undef, splat (i64 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4i64 = sdiv <4 x i64> undef, splat (i64 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i64 = sdiv <8 x i64> undef, splat (i64 7)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = sdiv i32 undef, 7
-; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = sdiv <4 x i32> undef, <i32 7, i32 7, i32 7, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i32 = sdiv <8 x i32> undef, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i32 = sdiv <16 x i32> undef, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = sdiv <4 x i32> undef, splat (i32 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i32 = sdiv <8 x i32> undef, splat (i32 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i32 = sdiv <16 x i32> undef, splat (i32 7)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = sdiv i16 undef, 7
-; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8i16 = sdiv <8 x i16> undef, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i16 = sdiv <16 x i16> undef, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i16 = sdiv <32 x i16> undef, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8i16 = sdiv <8 x i16> undef, splat (i16 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i16 = sdiv <16 x i16> undef, splat (i16 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i16 = sdiv <32 x i16> undef, splat (i16 7)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = sdiv i8 undef, 7
-; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16i8 = sdiv <16 x i8> undef, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i8 = sdiv <32 x i8> undef, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64i8 = sdiv <64 x i8> undef, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16i8 = sdiv <16 x i8> undef, splat (i8 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i8 = sdiv <32 x i8> undef, splat (i8 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64i8 = sdiv <64 x i8> undef, splat (i8 7)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%I128 = sdiv i128 undef, 7
@@ -238,21 +238,21 @@ define i32 @udiv_uniformconst() {
; CHECK-LABEL: 'udiv_uniformconst'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I128 = udiv i128 undef, 7
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I64 = udiv i64 undef, 7
-; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2i64 = udiv <2 x i64> undef, <i64 7, i64 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4i64 = udiv <4 x i64> undef, <i64 7, i64 7, i64 7, i64 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i64 = udiv <8 x i64> undef, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2i64 = udiv <2 x i64> undef, splat (i64 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4i64 = udiv <4 x i64> undef, splat (i64 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i64 = udiv <8 x i64> undef, splat (i64 7)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = udiv i32 undef, 7
-; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = udiv <4 x i32> undef, <i32 7, i32 7, i32 7, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i32 = udiv <8 x i32> undef, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i32 = udiv <16 x i32> undef, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = udiv <4 x i32> undef, splat (i32 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i32 = udiv <8 x i32> undef, splat (i32 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i32 = udiv <16 x i32> undef, splat (i32 7)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = udiv i16 undef, 7
-; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8i16 = udiv <8 x i16> undef, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i16 = udiv <16 x i16> undef, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i16 = udiv <32 x i16> undef, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8i16 = udiv <8 x i16> undef, splat (i16 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i16 = udiv <16 x i16> undef, splat (i16 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i16 = udiv <32 x i16> undef, splat (i16 7)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = udiv i8 undef, 7
-; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16i8 = udiv <16 x i8> undef, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i8 = udiv <32 x i8> undef, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64i8 = udiv <64 x i8> undef, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16i8 = udiv <16 x i8> undef, splat (i8 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i8 = udiv <32 x i8> undef, splat (i8 7)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64i8 = udiv <64 x i8> undef, splat (i8 7)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%I128 = udiv i128 undef, 7
@@ -376,21 +376,21 @@ define i32 @sdiv_uniformconstpow2() {
; CHECK-LABEL: 'sdiv_uniformconstpow2'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I128 = sdiv i128 undef, 16
; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I64 = sdiv i64 undef, 16
-; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V2i64 = sdiv <2 x i64> undef, <i64 16, i64 16>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V4i64 = sdiv <4 x i64> undef, <i64 16, i64 16, i64 16, i64 16>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %V8i64 = sdiv <8 x i64> undef, <i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V2i64 = sdiv <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V4i64 = sdiv <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %V8i64 = sdiv <8 x i64> undef, splat (i64 16)
; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I32 = sdiv i32 undef, 16
-; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V4i32 = sdiv <4 x i32> undef, <i32 16, i32 16, i32 16, i32 16>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 54 for instruction: %V8i32 = sdiv <8 x i32> undef, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 108 for instruction: %V16i32 = sdiv <16 x i32> undef, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V4i32 = sdiv <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 54 for instruction: %V8i32 = sdiv <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 108 for instruction: %V16i32 = sdiv <16 x i32> undef, splat (i32 16)
; CHECK-NEXT: Cost Model: Found an estimated cos...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/112548
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