[llvm] f113a66 - [ARM] Fix warnings in ARMAsmParser.cpp and ARMDisassembler.cpp (#112507)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 16 04:49:38 PDT 2024
Author: Karl-Johan Karlsson
Date: 2024-10-16T13:49:34+02:00
New Revision: f113a66c29b17e4937ff5d0ab67dc087fa6ee27e
URL: https://github.com/llvm/llvm-project/commit/f113a66c29b17e4937ff5d0ab67dc087fa6ee27e
DIFF: https://github.com/llvm/llvm-project/commit/f113a66c29b17e4937ff5d0ab67dc087fa6ee27e.diff
LOG: [ARM] Fix warnings in ARMAsmParser.cpp and ARMDisassembler.cpp (#112507)
Fix gcc warnings like:
ARMAsmParser.cpp:7168:46: warning: enumeral and non-enumeral type in
conditional expression [-Wextra]
Added:
Modified:
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 75fb90477f8854..b908e4f367e1a3 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2532,14 +2532,14 @@ class ARMOperand : public MCParsedAsmOperand {
void addCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
- unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
+ unsigned RegNum = getCondCode() == ARMCC::AL ? ARM::NoRegister : ARM::CPSR;
Inst.addOperand(MCOperand::createReg(RegNum));
}
void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
- unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
+ unsigned RegNum = getVPTPred() == ARMVCC::None ? ARM::NoRegister : ARM::P0;
Inst.addOperand(MCOperand::createReg(RegNum));
Inst.addOperand(MCOperand::createReg(0));
}
@@ -7164,8 +7164,8 @@ bool ARMAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
// Add the carry setting operand, if necessary.
if (CanAcceptCarrySet && CarrySetting) {
SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
- Operands.push_back(
- ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, Loc, *this));
+ Operands.push_back(ARMOperand::CreateCCOut(
+ CarrySetting ? ARM::CPSR : ARM::NoRegister, Loc, *this));
}
// Add the predication code operand, if necessary.
@@ -10372,7 +10372,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
case ARM::t2ASRri:
if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
isARMLowRegister(Inst.getOperand(1).getReg()) &&
- Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(5).getReg() ==
+ (inITBlock() ? ARM::NoRegister : ARM::CPSR) &&
!HasWideQualifier) {
unsigned NewOpc;
switch (Inst.getOpcode()) {
@@ -10422,14 +10423,14 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : ARM::NoRegister));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // Rm
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
if (!isNarrow)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : ARM::NoRegister));
Inst = TmpInst;
return true;
}
@@ -10475,7 +10476,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow && !isMov)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : ARM::NoRegister));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
if (newOpc != ARM::t2RRX && !isMov)
TmpInst.addOperand(MCOperand::createImm(Amount));
@@ -10483,7 +10484,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.addOperand(Inst.getOperand(4));
if (!isNarrow)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : ARM::NoRegister));
Inst = TmpInst;
return true;
}
@@ -10684,7 +10685,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
!isARMLowRegister(Inst.getOperand(0).getReg()) ||
(Inst.getOperand(2).isImm() &&
(unsigned)Inst.getOperand(2).getImm() > 255) ||
- Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
+ Inst.getOperand(5).getReg() !=
+ (inITBlock() ? ARM::NoRegister : ARM::CPSR) ||
HasWideQualifier)
break;
MCInst TmpInst;
@@ -10852,7 +10854,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
(Inst.getOperand(1).isImm() &&
(unsigned)Inst.getOperand(1).getImm() <= 255) &&
- Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(4).getReg() ==
+ (inITBlock() ? ARM::NoRegister : ARM::CPSR) &&
!HasWideQualifier) {
// The operands aren't in the same order for tMOVi8...
MCInst TmpInst;
@@ -10993,7 +10996,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
isARMLowRegister(Inst.getOperand(2).getReg())) &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
- Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(5).getReg() ==
+ (inITBlock() ? ARM::NoRegister : ARM::CPSR) &&
!HasWideQualifier) {
unsigned NewOpc;
switch (Inst.getOpcode()) {
@@ -11029,7 +11033,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
isARMLowRegister(Inst.getOperand(2).getReg())) &&
(Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
- Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(5).getReg() ==
+ (inITBlock() ? ARM::NoRegister : ARM::CPSR) &&
!HasWideQualifier) {
unsigned NewOpc;
switch (Inst.getOpcode()) {
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 93b74905fc59fc..fa5dd10cfdaa06 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -894,12 +894,13 @@ void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const {
MCID.operands()[i].RegClass == ARM::CCRRegClassID) {
if (i > 0 && MCID.operands()[i - 1].isPredicate())
continue;
- MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I,
+ MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR));
return;
}
}
- MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR));
}
bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {
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