[llvm] [RISCV] Separate HW/SW shadow stack on RISC-V (PR #112478)

[Ming-Yi Lai via llvm-commits]

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@@ -73,7 +77,7 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
     return;
 
   const RISCVInstrInfo *TII = STI.getInstrInfo();
-  if (!STI.hasForcedSWShadowStack() && STI.hasStdExtZicfiss()) {
+  if (HasHWShadowStack) {
     BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
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mylai-mtk wrote:

I would have concern of using `SSPUSH` here since the only check performed here is `STI.hasStdExtZimop()`, but in tablegen, the predicate of `SSPUSH` (and friends) is `HasStdExtZicfiss`.

https://github.com/llvm/llvm-project/pull/112478