[llvm] [ARM] Fix warnings in ARMAsmParser.cpp and ARMDisassembler.cpp (PR #112507)
Karl-Johan Karlsson via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 16 02:24:31 PDT 2024
https://github.com/karka228 created https://github.com/llvm/llvm-project/pull/112507
Fix gcc warnings like:
ARMAsmParser.cpp:7168:46: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
>From 6fa7c745c9de87c0e2444bd7c64e14c80a680e83 Mon Sep 17 00:00:00 2001
From: Karl-Johan Karlsson <karl-johan.karlsson at ericsson.com>
Date: Wed, 16 Oct 2024 11:17:41 +0200
Subject: [PATCH] [ARM] Fix warnings in ARMAsmParser.cpp and
ARMDisassembler.cpp
Fix gcc warnings like:
ARMAsmParser.cpp:7168:46: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
---
.../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 24 +++++++++----------
.../ARM/Disassembler/ARMDisassembler.cpp | 4 ++--
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 75fb90477f8854..0623a973dfd075 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2532,14 +2532,14 @@ class ARMOperand : public MCParsedAsmOperand {
void addCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
- unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
+ unsigned RegNum = getCondCode() == ARMCC::AL ? 0: (unsigned)ARM::CPSR;
Inst.addOperand(MCOperand::createReg(RegNum));
}
void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
- unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
+ unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: (unsigned)ARM::P0;
Inst.addOperand(MCOperand::createReg(RegNum));
Inst.addOperand(MCOperand::createReg(0));
}
@@ -7165,7 +7165,7 @@ bool ARMAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
if (CanAcceptCarrySet && CarrySetting) {
SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
Operands.push_back(
- ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, Loc, *this));
+ ARMOperand::CreateCCOut(CarrySetting ? (unsigned)ARM::CPSR : 0, Loc, *this));
}
// Add the predication code operand, if necessary.
@@ -10372,7 +10372,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
case ARM::t2ASRri:
if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
isARMLowRegister(Inst.getOperand(1).getReg()) &&
- Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(5).getReg() == (inITBlock() ? 0 : (unsigned)ARM::CPSR) &&
!HasWideQualifier) {
unsigned NewOpc;
switch (Inst.getOpcode()) {
@@ -10422,14 +10422,14 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsr ? (unsigned)ARM::CPSR : 0));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // Rm
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
if (!isNarrow)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsr ? (unsigned)ARM::CPSR : 0));
Inst = TmpInst;
return true;
}
@@ -10475,7 +10475,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow && !isMov)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsi ? (unsigned)ARM::CPSR : 0));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
if (newOpc != ARM::t2RRX && !isMov)
TmpInst.addOperand(MCOperand::createImm(Amount));
@@ -10483,7 +10483,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.addOperand(Inst.getOperand(4));
if (!isNarrow)
TmpInst.addOperand(MCOperand::createReg(
- Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
+ Inst.getOpcode() == ARM::t2MOVSsi ? (unsigned)ARM::CPSR : 0));
Inst = TmpInst;
return true;
}
@@ -10684,7 +10684,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
!isARMLowRegister(Inst.getOperand(0).getReg()) ||
(Inst.getOperand(2).isImm() &&
(unsigned)Inst.getOperand(2).getImm() > 255) ||
- Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
+ Inst.getOperand(5).getReg() != (inITBlock() ? 0 : (unsigned)ARM::CPSR) ||
HasWideQualifier)
break;
MCInst TmpInst;
@@ -10852,7 +10852,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
(Inst.getOperand(1).isImm() &&
(unsigned)Inst.getOperand(1).getImm() <= 255) &&
- Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(4).getReg() == (inITBlock() ? 0 : (unsigned)ARM::CPSR) &&
!HasWideQualifier) {
// The operands aren't in the same order for tMOVi8...
MCInst TmpInst;
@@ -10993,7 +10993,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
isARMLowRegister(Inst.getOperand(2).getReg())) &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
- Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(5).getReg() == (inITBlock() ? 0 : (unsigned)ARM::CPSR) &&
!HasWideQualifier) {
unsigned NewOpc;
switch (Inst.getOpcode()) {
@@ -11029,7 +11029,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
isARMLowRegister(Inst.getOperand(2).getReg())) &&
(Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
- Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
+ Inst.getOperand(5).getReg() == (inITBlock() ? 0 : (unsigned)ARM::CPSR) &&
!HasWideQualifier) {
unsigned NewOpc;
switch (Inst.getOpcode()) {
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 93b74905fc59fc..8c348c07aeacff 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -894,12 +894,12 @@ void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const {
MCID.operands()[i].RegClass == ARM::CCRRegClassID) {
if (i > 0 && MCID.operands()[i - 1].isPredicate())
continue;
- MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? 0 : (unsigned)ARM::CPSR));
return;
}
}
- MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? 0 : (unsigned)ARM::CPSR));
}
bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {
More information about the llvm-commits
mailing list