[llvm] [RISCV][VLOPT] Add support for widening integer mul-add instructions (PR #112219)

[Craig Topper via llvm-commits]

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@@ -422,8 +422,8 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
   case RISCV::VWSUB_WX:
   // Vector Widening Integer Multiply-Add Instructions
   // Destination EEW=2*SEW and EMUL=2*LMUL. Source EEW=SEW and EMUL=LMUL.
-  // Even though the add is a 2*SEW addition, the operands of the add are the
-  // Dest which is 2*SEW and the result of the multiply which is 2*SEW.
+  // A SEW-bit*SEW-bit multiply of the sources forms a 2*SEW-bit value, which
+  // is then added to the 2*SEW-bit Dest.
   case RISCV::VWMACCU_VV:
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topperc wrote:

The HasPassthru check below is wrong. MACC instructions don't have separate passthru because they always have 3 arithmetic operands.

https://github.com/llvm/llvm-project/pull/112219