[llvm] [RISCV] Promote fixed-length bf16 arith vector ops with zvfbfmin (PR #112393)

[Craig Topper via llvm-commits]

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@@ -1380,6 +1380,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
               {ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
               Custom);
           // TODO: Promote to fp32.
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topperc wrote:

Remove the TODO?

https://github.com/llvm/llvm-project/pull/112393