[llvm] [RISCV] Promote fixed-length bf16 arith vector ops with zvfbfmin (PR #112393)

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git-clang-format --diff 2a0073f6b50e8ae8f08dcf9c29d90503ac7816ae 5d0541637fc972e76113931723a3154d0cde03d5 --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ae61b03a4a..3c4149b455 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1380,7 +1380,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
               {ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
               Custom);
           // TODO: Promote to fp32.
-	  MVT F32VecVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
+          MVT F32VecVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
           // Don't promote f16 vector operations to f32 if f32 vector type is
           // not legal.
           // TODO: could split the f16 vector into two vectors and do promotion.

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https://github.com/llvm/llvm-project/pull/112393