[llvm] AMDGPU/GlobalISel: Run redundant_and combine in RegBankCombiner (PR #112353)

[Petar Avramovic via llvm-commits]

================
@@ -178,7 +178,7 @@ void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg,
   if (MRI.constrainRegAttrs(ToReg, FromReg))
     MRI.replaceRegWith(FromReg, ToReg);
   else
-    Builder.buildCopy(ToReg, FromReg);
+    Builder.buildCopy(FromReg, ToReg);
----------------
petar-avramovic wrote:

It is from weird bfe lowering, bfe sets reg clases on all its inputs as it is inst-selected in regbank-select
```
body:             |
  bb.1 (%ir-block.0):
    liveins: $sgpr2_sgpr3
  
    %2:sgpr(p4) = COPY $sgpr2_sgpr3
    %16:sgpr(s64) = G_CONSTANT i64 36
    %17:sgpr(p4) = nuw nusw G_PTR_ADD %2, %16(s64)
    %18:sgpr(p1) = G_LOAD %17(p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, align 4, addrspace 4)
    %20:sreg_32(s32) = G_CONSTANT i32 0
    %21:sgpr(s32) = G_CONSTANT i32 63
    %22:sgpr(s32) = G_AND %20, %21
    %23:sgpr(s32) = G_CONSTANT i32 16
    %24:sgpr(s32) = G_SHL %20, %23(s32)
    %25:sreg_32(s32) = G_OR %22, %24
    %19:sreg_32(s32) = S_BFE_U32 %20(s32), %25(s32), implicit-def $scc
    %26:vgpr(s32) = COPY %19(s32)
    %27:vgpr(p1) = COPY %18(p1)
    G_STORE %26(s32), %27(p1) :: (store (s32) into %ir.out.load, addrspace 1)
    S_ENDPGM 0
...
```


https://github.com/llvm/llvm-project/pull/112353