[llvm] [IR] Add support for `samesign` in `Operator::hasPoisonGeneratingFlags` (PR #112358)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 15 07:31:31 PDT 2024
https://github.com/dtcxzyw updated https://github.com/llvm/llvm-project/pull/112358
>From 3046d4846608f5e7f54b289f84e4d88fc03a386e Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 15 Oct 2024 21:21:56 +0800
Subject: [PATCH 1/3] [InstCombine] Add pre-commit tests. NFC.
---
llvm/test/Transforms/InstCombine/icmp.ll | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll
index ecf21b8a42cf50..c668d3b614dfe1 100644
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -5365,3 +5365,14 @@ define i1 @icmp_and_inv_pow2_or_zero_ne_0(i32 %A, i32 %B) {
%cmp = icmp ne i32 %and, 0
ret i1 %cmp
}
+
+define i1 @icmp_samesign_logical_and(i32 %In) {
+; CHECK-LABEL: @icmp_samesign_logical_and(
+; CHECK-NEXT: [[C2:%.*]] = icmp samesign eq i32 [[IN:%.*]], 1
+; CHECK-NEXT: ret i1 [[C2]]
+;
+ %c1 = icmp samesign sgt i32 %In, -1
+ %c2 = icmp samesign eq i32 %In, 1
+ %V = select i1 %c1, i1 %c2, i1 false
+ ret i1 %V
+}
>From d3e10685590aeeabb102b4e288ab44c55d024502 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 15 Oct 2024 21:39:41 +0800
Subject: [PATCH 2/3] [IR] Add support for `samesign` in
`Operator::hasPoisonGeneratingFlags`
---
llvm/lib/IR/Operator.cpp | 2 ++
llvm/test/Transforms/InstCombine/icmp.ll | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/IR/Operator.cpp b/llvm/lib/IR/Operator.cpp
index f93ff8f6fc8a25..199eb4d90f5565 100644
--- a/llvm/lib/IR/Operator.cpp
+++ b/llvm/lib/IR/Operator.cpp
@@ -50,6 +50,8 @@ bool Operator::hasPoisonGeneratingFlags() const {
if (auto *NNI = dyn_cast<PossiblyNonNegInst>(this))
return NNI->hasNonNeg();
return false;
+ case Instruction::ICmp:
+ return cast<ICmpInst>(this)->hasSameSign();
default:
if (const auto *FP = dyn_cast<FPMathOperator>(this))
return FP->hasNoNaNs() || FP->hasNoInfs();
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll
index c668d3b614dfe1..bfe70f992b8457 100644
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -5368,7 +5368,7 @@ define i1 @icmp_and_inv_pow2_or_zero_ne_0(i32 %A, i32 %B) {
define i1 @icmp_samesign_logical_and(i32 %In) {
; CHECK-LABEL: @icmp_samesign_logical_and(
-; CHECK-NEXT: [[C2:%.*]] = icmp samesign eq i32 [[IN:%.*]], 1
+; CHECK-NEXT: [[C2:%.*]] = icmp eq i32 [[IN:%.*]], 1
; CHECK-NEXT: ret i1 [[C2]]
;
%c1 = icmp samesign sgt i32 %In, -1
>From 3dd63d958ff015071172172ab3b159ee84547d48 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 15 Oct 2024 22:30:55 +0800
Subject: [PATCH 3/3] [InstCombine] Add a test for logical or
---
llvm/test/Transforms/InstCombine/icmp.ll | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll
index bfe70f992b8457..5e80134b153be7 100644
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -5376,3 +5376,14 @@ define i1 @icmp_samesign_logical_and(i32 %In) {
%V = select i1 %c1, i1 %c2, i1 false
ret i1 %V
}
+
+define i1 @icmp_samesign_logical_or(i32 %In) {
+; CHECK-LABEL: @icmp_samesign_logical_or(
+; CHECK-NEXT: [[V:%.*]] = icmp ne i32 [[IN:%.*]], 1
+; CHECK-NEXT: ret i1 [[V]]
+;
+ %c1 = icmp samesign slt i32 %In, 0
+ %c2 = icmp samesign ne i32 %In, 1
+ %V = select i1 %c1, i1 true, i1 %c2
+ ret i1 %V
+}
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