[llvm] 043f066 - [RISCV][VLOPT] Fix operand check in isVectorOpUsedAsScalarOp (#112253)

[via llvm-commits]

Author: Luke Lau
Date: 2024-10-15T15:10:26+01:00
New Revision: 043f066a647334195da41d7f5fd2a8400d7e4c91

URL: https://github.com/llvm/llvm-project/commit/043f066a647334195da41d7f5fd2a8400d7e4c91
DIFF: https://github.com/llvm/llvm-project/commit/043f066a647334195da41d7f5fd2a8400d7e4c91.diff

LOG: [RISCV][VLOPT] Fix operand check in isVectorOpUsedAsScalarOp (#112253)

A reduction instruction always has a passthru operand, so the scalar
operand should always be vs1 which is at index 3.

Even though the destination operand is also scalar, I think the passthru
will need to preserve all elements so I haven't included it.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
    llvm/test/CodeGen/RISCV/rvv/vl-opt.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 1a9084f8b6cb2b..8a4dd70d961f8b 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -611,10 +611,8 @@ static bool isVectorOpUsedAsScalarOp(MachineOperand &MO) {
   case RISCV::VFREDOSUM_VS:
   case RISCV::VFREDUSUM_VS:
   case RISCV::VFWREDOSUM_VS:
-  case RISCV::VFWREDUSUM_VS: {
-    bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(MI->getDesc());
-    return HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 3;
-  }
+  case RISCV::VFWREDUSUM_VS:
+    return MO.getOperandNo() == 3;
   default:
     return false;
   }

diff  --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index 59a472c73a4624..010e3ca642269b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -16,3 +16,20 @@ body: |
     %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
     %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */
 ...
+---
+name: vredsum_vv_user
+body: |
+  bb.0:
+    liveins: $x1
+    ; CHECK-LABEL: name: vredsum_vv_user
+    ; CHECK: liveins: $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %vl:gprnox0 = COPY $x1
+    ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E64 $noreg, %x, $noreg, -1, 6 /* e64 */, 0 /* tu, mu */
+    ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 /* tu, mu */
+    %vl:gprnox0 = COPY $x1
+    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
+    %y:vr = PseudoVREDSUM_VS_M1_E64 $noreg, %x, $noreg, -1, 6 /* e64 */, 0 /* tu, mu */
+    %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 /* tu, mu */
+...