[llvm] [SelectionDAG] Add preliminary plumbing for `samesign` flag (PR #112354)

[Antonio Frighetto via llvm-commits]

https://github.com/antoniofrighetto created https://github.com/llvm/llvm-project/pull/112354

Extend recently-added poison-generating IR flag to codegen as well.

I think there are some other places in TargetLowering (e.g., `LegalizeSetCCCondCode`) where the flag should be cleared, welcoming directions (also maybe besides `SDNodeFlags`, it can be added to `MIFlag` directly here).

>From 276ebf5817594de082977bf67f3afa5f0f440ea7 Mon Sep 17 00:00:00 2001
From: Antonio Frighetto <me at antoniofrighetto.com>
Date: Tue, 15 Oct 2024 15:08:25 +0200
Subject: [PATCH] [SelectionDAG] Add preliminary plumbing for `samesign`

Extend recently-added poison-generating IR flag to codegen as well.
---
 llvm/include/llvm/CodeGen/SelectionDAGNodes.h      | 14 +++++++++-----
 .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp   |  4 ++++
 .../CodeGen/SelectionDAG/SelectionDAGDumper.cpp    |  3 +++
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp   |  8 +++++++-
 4 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index 639e9311977502..bad19173683101 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -382,6 +382,7 @@ struct SDNodeFlags {
   bool NoSignedWrap : 1;
   bool Exact : 1;
   bool Disjoint : 1;
+  bool SameSign : 1;
   bool NonNeg : 1;
   bool NoNaNs : 1;
   bool NoInfs : 1;
@@ -404,10 +405,10 @@ struct SDNodeFlags {
   /// Default constructor turns off all optimization flags.
   SDNodeFlags()
       : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false),
-        Disjoint(false), NonNeg(false), NoNaNs(false), NoInfs(false),
-        NoSignedZeros(false), AllowReciprocal(false), AllowContract(false),
-        ApproximateFuncs(false), AllowReassociation(false), NoFPExcept(false),
-        Unpredictable(false) {}
+        Disjoint(false), SameSign(false), NonNeg(false), NoNaNs(false),
+        NoInfs(false), NoSignedZeros(false), AllowReciprocal(false),
+        AllowContract(false), ApproximateFuncs(false),
+        AllowReassociation(false), NoFPExcept(false), Unpredictable(false) {}
 
   /// Propagate the fast-math-flags from an IR FPMathOperator.
   void copyFMF(const FPMathOperator &FPMO) {
@@ -425,6 +426,7 @@ struct SDNodeFlags {
   void setNoSignedWrap(bool b) { NoSignedWrap = b; }
   void setExact(bool b) { Exact = b; }
   void setDisjoint(bool b) { Disjoint = b; }
+  void setSameSign(bool b) { SameSign = b; }
   void setNonNeg(bool b) { NonNeg = b; }
   void setNoNaNs(bool b) { NoNaNs = b; }
   void setNoInfs(bool b) { NoInfs = b; }
@@ -441,6 +443,7 @@ struct SDNodeFlags {
   bool hasNoSignedWrap() const { return NoSignedWrap; }
   bool hasExact() const { return Exact; }
   bool hasDisjoint() const { return Disjoint; }
+  bool hasSameSign() const { return SameSign; }
   bool hasNonNeg() const { return NonNeg; }
   bool hasNoNaNs() const { return NoNaNs; }
   bool hasNoInfs() const { return NoInfs; }
@@ -473,6 +476,7 @@ struct SDNodeFlags {
     NoSignedWrap &= Flags.NoSignedWrap;
     Exact &= Flags.Exact;
     Disjoint &= Flags.Disjoint;
+    SameSign &= Flags.SameSign;
     NonNeg &= Flags.NonNeg;
     NoNaNs &= Flags.NoNaNs;
     NoInfs &= Flags.NoInfs;
@@ -1032,7 +1036,7 @@ END_TWO_BYTE_PACK()
     SDNodeFlags Flags = getFlags();
     return Flags.hasNoUnsignedWrap() || Flags.hasNoSignedWrap() ||
            Flags.hasExact() || Flags.hasDisjoint() || Flags.hasNonNeg() ||
-           Flags.hasNoNaNs() || Flags.hasNoInfs();
+           Flags.hasNoNaNs() || Flags.hasNoInfs() || Flags.hasSameSign();
   }
 
   void setCFIType(uint32_t Type) { CFIType = Type; }
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 805b8ecf009598..35ea9419f2dd1a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3640,6 +3640,10 @@ void SelectionDAGBuilder::visitICmp(const ICmpInst &I) {
   SDValue Op2 = getValue(I.getOperand(1));
   ISD::CondCode Opcode = getICmpCondCode(predicate);
 
+  SDNodeFlags Flags;
+  Flags.setSameSign(I.hasSameSign());
+  SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
+
   auto &TLI = DAG.getTargetLoweringInfo();
   EVT MemVT =
       TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index 56fc538172f9fc..24fc83b422147f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -651,6 +651,9 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
   if (getFlags().hasDisjoint())
     OS << " disjoint";
 
+  if (getFlags().hasSameSign())
+    OS << " samesign";
+
   if (getFlags().hasNonNeg())
     OS << " nneg";
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 40f030d7b936f7..43e6a43e820b5a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1703,6 +1703,7 @@ bool TargetLowering::SimplifyDemandedBits(
   case ISD::SETCC: {
     SDValue Op0 = Op.getOperand(0);
     SDValue Op1 = Op.getOperand(1);
+    SDNodeFlags Flags = Op.getNode()->getFlags();
     ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
     // If (1) we only need the sign-bit, (2) the setcc operands are the same
     // width as the setcc result, and (3) the result of a setcc conforms to 0 or
@@ -1716,8 +1717,13 @@ bool TargetLowering::SimplifyDemandedBits(
       // if we don't care about FP signed-zero. The use of SETLT with FP means
       // that we don't care about NaNs.
       if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
-          (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode())))
+          (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode()))) {
+        if (Flags.hasSameSign()) {
+          Flags.setSameSign(false);
+          Op->setFlags(Flags);
+        }
         return TLO.CombineTo(Op, Op0);
+      }
 
       // TODO: Should we check for other forms of sign-bit comparisons?
       // Examples: X <= -1, X >= 0