[llvm] [CodeGen] [AMDGPU] Attempt DAGCombine for fmul with select to ldexp (PR #111109)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 15 00:48:00 PDT 2024
================
@@ -14476,6 +14477,60 @@ SDValue SITargetLowering::performFDivCombine(SDNode *N,
return SDValue();
}
+SDValue SITargetLowering::performFMulCombine(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ SelectionDAG &DAG = DCI.DAG;
+ EVT VT = N->getValueType(0);
+ EVT i32VT = VT.changeElementType(MVT::i32);
+
+ SDLoc SL(N);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+
+ // ldexp(x, zext(i1 y)) -> fmul x, (select y, 2.0, 1.0)
+ // ldexp(x, sext(i1 y)) -> fmul x, (select y, 0.5, 1.0)
+ //
+ // The above mentioned ldexp folding works fine for
+ // bf16/f32, but as for f64 it creates f64 select which
+ // is costly to materialize as compared to f64 ldexp
+ // so here we undo the transform for f64 datatype.
+ // Also in case of f16, its cheaper to materialize inline
+ // 32 bit-constant (via ldexp use) rather than using fmul.
----------------
arsenm wrote:
Comment is verbose. Just state that it's cheaper to use i32 inline constants than to materialize f16 or f64 values
https://github.com/llvm/llvm-project/pull/111109
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