[llvm] 5462725 - [RISCV] Rename rs1_wb to rd in some C instructions. NFC (#112269)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 14 20:49:48 PDT 2024
Author: Craig Topper
Date: 2024-10-14T20:49:46-07:00
New Revision: 5462725e0cfc40ed276f68fe9f639b072cb14700
URL: https://github.com/llvm/llvm-project/commit/5462725e0cfc40ed276f68fe9f639b072cb14700
DIFF: https://github.com/llvm/llvm-project/commit/5462725e0cfc40ed276f68fe9f639b072cb14700.diff
LOG: [RISCV] Rename rs1_wb to rd in some C instructions. NFC (#112269)
The spec refers to the field as rd'/rs1' so we might as well name the
destination rd.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 7e032014d05044..e8c4860fd3e55e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -279,9 +279,9 @@ class Bcz<bits<3> funct3, string OpcodeStr,
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class Shift_right<bits<2> funct2, string OpcodeStr, RegisterClass cls,
Operand ImmOpnd>
- : RVInst16CB<0b100, 0b01, (outs cls:$rs1_wb), (ins cls:$rs1, ImmOpnd:$imm),
+ : RVInst16CB<0b100, 0b01, (outs cls:$rd), (ins cls:$rs1, ImmOpnd:$imm),
OpcodeStr, "$rs1, $imm"> {
- let Constraints = "$rs1 = $rs1_wb";
+ let Constraints = "$rs1 = $rd";
let Inst{12} = imm{5};
let Inst{11-10} = funct2;
let Inst{6-2} = imm{4-0};
@@ -479,10 +479,10 @@ def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>,
Sched<[WriteShiftImm, ReadShiftImm]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm),
+def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rd), (ins GPRC:$rs1, simm6:$imm),
"c.andi", "$rs1, $imm">,
Sched<[WriteIALU, ReadIALU]> {
- let Constraints = "$rs1 = $rs1_wb";
+ let Constraints = "$rs1 = $rd";
let Inst{12} = imm{5};
let Inst{11-10} = 0b10;
let Inst{6-2} = imm{4-0};
@@ -582,11 +582,11 @@ def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
"c.jalr", "$rs1">, Sched<[WriteJalr, ReadJalr]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rs1_wb),
+def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rd),
(ins GPRNoX0:$rs1, GPRNoX0:$rs2),
"c.add", "$rs1, $rs2">,
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
- let Constraints = "$rs1 = $rs1_wb";
+ let Constraints = "$rs1 = $rd";
}
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
@@ -680,11 +680,11 @@ def C_MV_HINT : RVInst16CR<0b1000, 0b10, (outs GPRX0:$rs1), (ins GPRNoX0:$rs2),
let DecoderMethod = "decodeRVCInstrRdRs2";
}
-def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rs1_wb),
+def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rd),
(ins GPRX0:$rs1, GPRNoX0:$rs2),
"c.add", "$rs1, $rs2">,
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
- let Constraints = "$rs1 = $rs1_wb";
+ let Constraints = "$rs1 = $rd";
let Inst{11-7} = 0;
let DecoderMethod = "decodeRVCInstrRdRs1Rs2";
}
@@ -707,21 +707,21 @@ def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
let Inst{12} = 0;
}
-def C_SRLI64_HINT : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb),
+def C_SRLI64_HINT : RVInst16CB<0b100, 0b01, (outs GPRC:$rd),
(ins GPRC:$rs1),
"c.srli64", "$rs1">,
Sched<[WriteShiftImm, ReadShiftImm]> {
- let Constraints = "$rs1 = $rs1_wb";
+ let Constraints = "$rs1 = $rd";
let Inst{6-2} = 0;
let Inst{11-10} = 0b00;
let Inst{12} = 0;
}
-def C_SRAI64_HINT : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb),
+def C_SRAI64_HINT : RVInst16CB<0b100, 0b01, (outs GPRC:$rd),
(ins GPRC:$rs1),
"c.srai64", "$rs1">,
Sched<[WriteShiftImm, ReadShiftImm]> {
- let Constraints = "$rs1 = $rs1_wb";
+ let Constraints = "$rs1 = $rd";
let Inst{6-2} = 0;
let Inst{11-10} = 0b01;
let Inst{12} = 0;
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