[llvm] [RISCV] Add missing assembler test case for c.addi zero, 0. NFC (PR #112291)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/112291

This is an assembly only alias for c.nop.

>From 5a2af7aad06ea137175b73fbadd759832400e24f Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 14 Oct 2024 18:22:02 -0700
Subject: [PATCH] [RISCV] Add missing assembler test case for c.addi zero, 0.
 NFC

This is an alias for c.nop.
---
 llvm/test/MC/RISCV/rv32c-valid.s | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/llvm/test/MC/RISCV/rv32c-valid.s b/llvm/test/MC/RISCV/rv32c-valid.s
index c9e9b0053173be..bcdf27a2ba783b 100644
--- a/llvm/test/MC/RISCV/rv32c-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-valid.s
@@ -147,6 +147,11 @@ c.sub a4, a5
 # CHECK-ASM: encoding: [0x01,0x00]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
 c.nop
+# CHECK-ASM: c.addi zero, 0
+# CHECK-OBJ: c.nop
+# CHECK-ASM: encoding: [0x01,0x00]
+# CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
+c.addi x0, 0
 # CHECK-ASM-AND-OBJ: c.ebreak
 # CHECK-ASM: encoding: [0x02,0x90]
 # CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}