[llvm] 1c17484 - [RISCV] Use RVInst16CB for C_SRLI64_HINT and C_SRAI64_HINT. (#112250)

[via llvm-commits]

Author: Craig Topper
Date: 2024-10-14T15:25:29-07:00
New Revision: 1c17484e107523af2583dd62537902202ce8f2e7

URL: https://github.com/llvm/llvm-project/commit/1c17484e107523af2583dd62537902202ce8f2e7
DIFF: https://github.com/llvm/llvm-project/commit/1c17484e107523af2583dd62537902202ce8f2e7.diff

LOG: [RISCV] Use RVInst16CB for C_SRLI64_HINT and C_SRAI64_HINT. (#112250)

c.srli(64) and c.srai(64) are encoded differently than c.slli(64). The
former have a 3-bit register, while the latter has a 5-bit register.
c.srli and c.srai already use RVInst16CB.

The "let Inst{11-10} =" prevented this from causing any functional
issues by dropping the upper 2 bits of the register. The ins/outs list
uses GPRC so the register class is constrained.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index d468fb2a6c494c..7e032014d05044 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -707,23 +707,23 @@ def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
   let Inst{12} = 0;
 }
 
-def C_SRLI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
-                               (ins GPRC:$rd),
-                               "c.srli64", "$rd">,
+def C_SRLI64_HINT : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb),
+                               (ins GPRC:$rs1),
+                               "c.srli64", "$rs1">,
                     Sched<[WriteShiftImm, ReadShiftImm]> {
-  let Constraints = "$rd = $rd_wb";
+  let Constraints = "$rs1 = $rs1_wb";
   let Inst{6-2} = 0;
-  let Inst{11-10} = 0;
+  let Inst{11-10} = 0b00;
   let Inst{12} = 0;
 }
 
-def C_SRAI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
-                               (ins GPRC:$rd),
-                               "c.srai64", "$rd">,
+def C_SRAI64_HINT : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb),
+                               (ins GPRC:$rs1),
+                               "c.srai64", "$rs1">,
                     Sched<[WriteShiftImm, ReadShiftImm]> {
-  let Constraints = "$rd = $rd_wb";
+  let Constraints = "$rs1 = $rs1_wb";
   let Inst{6-2} = 0;
-  let Inst{11-10} = 1;
+  let Inst{11-10} = 0b01;
   let Inst{12} = 0;
 }