[llvm] db57fc4 - [RISCV][VLOPT] Fix passthru check in getOperandInfo (#112244)
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Mon Oct 14 12:54:21 PDT 2024
Author: Luke Lau
Date: 2024-10-14T20:54:17+01:00
New Revision: db57fc4edcfeecfa80356be4374fd28283632d7b
URL: https://github.com/llvm/llvm-project/commit/db57fc4edcfeecfa80356be4374fd28283632d7b
DIFF: https://github.com/llvm/llvm-project/commit/db57fc4edcfeecfa80356be4374fd28283632d7b.diff
LOG: [RISCV][VLOPT] Fix passthru check in getOperandInfo (#112244)
If a pseudo has a passthru, I believe the first source operand will have
operand no 2, not 1.
Added:
llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
Modified:
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index c48470ab707f10..089dc6c529193d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -128,6 +128,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVPreRAExpandPseudoPass(*PR);
initializeRISCVExpandPseudoPass(*PR);
initializeRISCVVectorPeepholePass(*PR);
+ initializeRISCVVLOptimizerPass(*PR);
initializeRISCVInsertVSETVLIPass(*PR);
initializeRISCVInsertReadWriteCSRPass(*PR);
initializeRISCVInsertWriteVXRMPass(*PR);
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 2720240cf52648..1a9084f8b6cb2b 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -431,7 +431,7 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
case RISCV::VWMACCSU_VV:
case RISCV::VWMACCSU_VX:
case RISCV::VWMACCUS_VX: {
- bool IsOp1 = HasPassthru ? MO.getOperandNo() == 1 : MO.getOperandNo() == 2;
+ bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1;
bool TwoTimes = IsMODef || IsOp1;
unsigned Log2EEW = TwoTimes ? MILog2SEW + 1 : MILog2SEW;
RISCVII::VLMUL EMUL =
@@ -467,7 +467,7 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
case RISCV::VNCLIP_WI:
case RISCV::VNCLIP_WV:
case RISCV::VNCLIP_WX: {
- bool IsOp1 = HasPassthru ? MO.getOperandNo() == 1 : MO.getOperandNo() == 2;
+ bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1;
bool TwoTimes = IsOp1;
unsigned Log2EEW = TwoTimes ? MILog2SEW + 1 : MILog2SEW;
RISCVII::VLMUL EMUL =
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
index 6e604d200a6279..1a01a9bf77cff5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
@@ -40,13 +40,20 @@ declare <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.nxv2i16(
iXLen);
define <vscale x 2 x i16> @intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, iXLen %2, <vscale x 2 x i32> %3, <vscale x 2 x i32> %4, <vscale x 2 x i16> %z) nounwind {
-; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwadd.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wv v8, v10, v12
-; CHECK-NEXT: ret
+; NOVLOPT-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16:
+; NOVLOPT: # %bb.0: # %entry
+; NOVLOPT-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; NOVLOPT-NEXT: vwadd.vv v10, v8, v9
+; NOVLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; NOVLOPT-NEXT: vnsrl.wv v8, v10, v12
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16:
+; VLOPT: # %bb.0: # %entry
+; VLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; VLOPT-NEXT: vwadd.vv v10, v8, v9
+; VLOPT-NEXT: vnsrl.wv v8, v10, v12
+; VLOPT-NEXT: ret
entry:
%c = sext <vscale x 2 x i16> %a to <vscale x 2 x i32>
%d = sext <vscale x 2 x i16> %b to <vscale x 2 x i32>
@@ -67,14 +74,22 @@ declare <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16(
iXLen, iXLen);
define <vscale x 2 x i16> @vnclip(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, iXLen %2, <vscale x 2 x i32> %3, <vscale x 2 x i32> %4, <vscale x 2 x i16> %z) nounwind {
-; CHECK-LABEL: vnclip:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwadd.vv v10, v8, v9
-; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vnclip.wv v8, v10, v12
-; CHECK-NEXT: ret
+; NOVLOPT-LABEL: vnclip:
+; NOVLOPT: # %bb.0: # %entry
+; NOVLOPT-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; NOVLOPT-NEXT: vwadd.vv v10, v8, v9
+; NOVLOPT-NEXT: csrwi vxrm, 0
+; NOVLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; NOVLOPT-NEXT: vnclip.wv v8, v10, v12
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vnclip:
+; VLOPT: # %bb.0: # %entry
+; VLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; VLOPT-NEXT: vwadd.vv v10, v8, v9
+; VLOPT-NEXT: csrwi vxrm, 0
+; VLOPT-NEXT: vnclip.wv v8, v10, v12
+; VLOPT-NEXT: ret
entry:
%c = sext <vscale x 2 x i16> %a to <vscale x 2 x i32>
%d = sext <vscale x 2 x i16> %b to <vscale x 2 x i32>
@@ -88,6 +103,3 @@ entry:
ret <vscale x 2 x i16> %x
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; NOVLOPT: {{.*}}
-; VLOPT: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
new file mode 100644
index 00000000000000..59a472c73a4624
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -0,0 +1,18 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s
+
+---
+name: vnsrl_wv_user
+body: |
+ bb.0:
+ liveins: $x1
+ ; CHECK-LABEL: name: vnsrl_wv_user
+ ; CHECK: liveins: $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %vl:gprnox0 = COPY $x1
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */
+ %vl:gprnox0 = COPY $x1
+ %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */
+...
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