[llvm] [RISCV][VLOPT] Fix passthru check in getOperandInfo (PR #112244)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 14 12:52:43 PDT 2024
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/112244
>From 200c33064f439ada0d8910af98602b1e08ce2283 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 14 Oct 2024 19:43:41 +0100
Subject: [PATCH 1/3] Precommit test
---
llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
new file mode 100644
index 00000000000000..e72f454746880c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -0,0 +1,18 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s
+
+---
+name: vnsrl_wv_user
+body: |
+ bb.0:
+ liveins: $x1
+ ; CHECK-LABEL: name: vnsrl_wv_user
+ ; CHECK: liveins: $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %vl:gprnox0 = COPY $x1
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */
+ %vl:gprnox0 = COPY $x1
+ %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */
+...
>From 7c4648249388e740193a6748a62f0707bea66b1d Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 14 Oct 2024 19:48:28 +0100
Subject: [PATCH 2/3] [RISCV][VLOPT] Fix passthru check in getOperandInfo
If a pseudo has a passthru, I believe the first source operand will be the second operand, not the first.
I've added an MIR test which should show how we're reading the wrong SEW, but in order to be able to use -run-pass=riscv-vl-optimizer I needed to initialize the pass in RISCVTargetMachine.cpp.
---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 1 +
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 4 ++--
llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 2 +-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index c48470ab707f10..089dc6c529193d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -128,6 +128,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVPreRAExpandPseudoPass(*PR);
initializeRISCVExpandPseudoPass(*PR);
initializeRISCVVectorPeepholePass(*PR);
+ initializeRISCVVLOptimizerPass(*PR);
initializeRISCVInsertVSETVLIPass(*PR);
initializeRISCVInsertReadWriteCSRPass(*PR);
initializeRISCVInsertWriteVXRMPass(*PR);
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index eb1f4df4ff7264..d4d66c4e1cec58 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -431,7 +431,7 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
case RISCV::VWMACCSU_VV:
case RISCV::VWMACCSU_VX:
case RISCV::VWMACCUS_VX: {
- bool IsOp1 = HasPassthru ? MO.getOperandNo() == 1 : MO.getOperandNo() == 2;
+ bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1;
bool TwoTimes = IsMODef || IsOp1;
unsigned Log2EEW = TwoTimes ? MILog2SEW + 1 : MILog2SEW;
RISCVII::VLMUL EMUL =
@@ -467,7 +467,7 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
case RISCV::VNCLIP_WI:
case RISCV::VNCLIP_WV:
case RISCV::VNCLIP_WX: {
- bool IsOp1 = HasPassthru ? MO.getOperandNo() == 1 : MO.getOperandNo() == 2;
+ bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1;
bool TwoTimes = IsOp1;
unsigned Log2EEW = TwoTimes ? MILog2SEW + 1 : MILog2SEW;
RISCVII::VLMUL EMUL =
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index e72f454746880c..59a472c73a4624 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -10,7 +10,7 @@ body: |
; CHECK: liveins: $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vl:gprnox0 = COPY $x1
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */
%vl:gprnox0 = COPY $x1
%x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
>From 676cc660a5fb3d8369ef37f437c8fb6f1f34094c Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 14 Oct 2024 20:52:14 +0100
Subject: [PATCH 3/3] Update another test
---
llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll | 48 ++++++++++++-------
1 file changed, 30 insertions(+), 18 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
index 6e604d200a6279..1a01a9bf77cff5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
@@ -40,13 +40,20 @@ declare <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.nxv2i16(
iXLen);
define <vscale x 2 x i16> @intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, iXLen %2, <vscale x 2 x i32> %3, <vscale x 2 x i32> %4, <vscale x 2 x i16> %z) nounwind {
-; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwadd.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wv v8, v10, v12
-; CHECK-NEXT: ret
+; NOVLOPT-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16:
+; NOVLOPT: # %bb.0: # %entry
+; NOVLOPT-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; NOVLOPT-NEXT: vwadd.vv v10, v8, v9
+; NOVLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; NOVLOPT-NEXT: vnsrl.wv v8, v10, v12
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16:
+; VLOPT: # %bb.0: # %entry
+; VLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; VLOPT-NEXT: vwadd.vv v10, v8, v9
+; VLOPT-NEXT: vnsrl.wv v8, v10, v12
+; VLOPT-NEXT: ret
entry:
%c = sext <vscale x 2 x i16> %a to <vscale x 2 x i32>
%d = sext <vscale x 2 x i16> %b to <vscale x 2 x i32>
@@ -67,14 +74,22 @@ declare <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16(
iXLen, iXLen);
define <vscale x 2 x i16> @vnclip(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, iXLen %2, <vscale x 2 x i32> %3, <vscale x 2 x i32> %4, <vscale x 2 x i16> %z) nounwind {
-; CHECK-LABEL: vnclip:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwadd.vv v10, v8, v9
-; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vnclip.wv v8, v10, v12
-; CHECK-NEXT: ret
+; NOVLOPT-LABEL: vnclip:
+; NOVLOPT: # %bb.0: # %entry
+; NOVLOPT-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; NOVLOPT-NEXT: vwadd.vv v10, v8, v9
+; NOVLOPT-NEXT: csrwi vxrm, 0
+; NOVLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; NOVLOPT-NEXT: vnclip.wv v8, v10, v12
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vnclip:
+; VLOPT: # %bb.0: # %entry
+; VLOPT-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; VLOPT-NEXT: vwadd.vv v10, v8, v9
+; VLOPT-NEXT: csrwi vxrm, 0
+; VLOPT-NEXT: vnclip.wv v8, v10, v12
+; VLOPT-NEXT: ret
entry:
%c = sext <vscale x 2 x i16> %a to <vscale x 2 x i32>
%d = sext <vscale x 2 x i16> %b to <vscale x 2 x i32>
@@ -88,6 +103,3 @@ entry:
ret <vscale x 2 x i16> %x
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; NOVLOPT: {{.*}}
-; VLOPT: {{.*}}
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