[llvm] 9c64b5e - [ARM] Simplify code with std::map::operator[] (NFC) (#112159)

[via llvm-commits]

Author: Kazu Hirata
Date: 2024-10-14T06:56:39-07:00
New Revision: 9c64b5e7591dd7f6f3dd3175a5e686f324c22978

URL: https://github.com/llvm/llvm-project/commit/9c64b5e7591dd7f6f3dd3175a5e686f324c22978
DIFF: https://github.com/llvm/llvm-project/commit/9c64b5e7591dd7f6f3dd3175a5e686f324c22978.diff

LOG: [ARM] Simplify code with std::map::operator[] (NFC) (#112159)

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 0921e364498186..51a5f895f341db 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6868,15 +6868,13 @@ bool ARMPipelinerLoopInfo::tooMuchRegisterPressure(SwingSchedulerDAG &SSD,
       if (MI->isPHI() && S.getKind() == SDep::Anti) {
         Register Reg = S.getReg();
         if (Reg.isVirtual())
-          CrossIterationNeeds.insert(std::make_pair(Reg.id(), IterNeed()))
-              .first->second.set(0);
+          CrossIterationNeeds[Reg.id()].set(0);
       } else if (S.isAssignedRegDep()) {
         int OStg = SMS.stageScheduled(S.getSUnit());
         if (OStg >= 0 && OStg != Stg) {
           Register Reg = S.getReg();
           if (Reg.isVirtual())
-            CrossIterationNeeds.insert(std::make_pair(Reg.id(), IterNeed()))
-                .first->second |= ((1 << (OStg - Stg)) - 1);
+            CrossIterationNeeds[Reg.id()] |= ((1 << (OStg - Stg)) - 1);
         }
       }
   }