[llvm] Promote pseudo opcodes from 32-bit to 64-bit for instructions that infer extsw elimination in PPCMIPeepholes pass (PR #85451)

[zhijian lin via llvm-commits]

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@@ -5234,6 +5234,224 @@ bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
 // We limit the max depth to track incoming values of PHIs or binary ops
 // (e.g. AND) to avoid excessive cost.
 const unsigned MAX_BINOP_DEPTH = 1;
+
+// This function will promote the instruction which defines the register `Reg`
+// in the parameter from a 32-bit to a 64-bit instruction if needed. The logic
+// used to check whether an instruction needs to be promoted or not is similar
+// to the logic used to check whether or not a defined register is sign or zero
+// extended within the function PPCInstrInfo::isSignOrZeroExtended.
+// Additionally, the `promoteInstr32To64ForElimEXTSW` function is recursive.
+// BinOpDepth does not count all of the recursions. The parameter BinOpDepth is
+// incremented  only when `promoteInstr32To64ForElimEXTSW` calls itself more
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diggerlin wrote:

Good Catch for AND8 .  the logic of BinOpDepth  is  come from function isSignOrZeroExtended(),  when the instructions(for example: AND, PHI, OR) which has two or more source registers , the instructions which defines these source registers also need to be promoted and so on , without increase the BinOpDepth  , it maybe have 2*2*2*2....recursions of promoteInstr32To64ForElimEXTSW.



https://github.com/llvm/llvm-project/pull/85451