[llvm] [LLVM][AArch64] Add register classes for Armv9.6 assembly (PR #111717)

[via llvm-commits]

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@@ -355,13 +362,43 @@ DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
   return Success;
 }
 
+template <unsigned Min, unsigned Max>
+static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
+                                         uint64_t Address,
+                                         const MCDisassembler *Decoder) {
+  unsigned Reg = RegNo * 2 + Min;
+  if (Reg < Min || Reg > Max || (Reg & 1))
+    return Fail;
+  unsigned Register =
+      AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);
+  Inst.addOperand(MCOperand::createReg(Register));
+  return Success;
+}
+
+template <unsigned Min, unsigned Max>
 static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
                                                 uint64_t Address,
                                                 const void *Decoder) {
-  if (RegNo * 2 > 30)
+  if ((RegNo * 2) + Min > Max)
+    return Fail;
+  unsigned Register =
+      AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2 +
+                                                                    Min);
+  Inst.addOperand(MCOperand::createReg(Register));
+  return Success;
+}
+
+// Zk Is the name of the control vector register Z20-Z23 or Z28-Z31, encoded in
+// the "K:Zk" fields. Z20-Z23 = 000, 001,010, 011  and Z28-Z31 = 100, 101, 110,
+// 111
+static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                             const MCDisassembler *Decoder) {
+  //  (Z28 => RegNo = 4) Z28 = 4 => Z28 + 24 = 28
----------------
Lukacma wrote:

This comment got me confused. Maybe something like this would make it clearer? 

`//  RegNo = 4 => Z28 = 28 (4 + 24)`

https://github.com/llvm/llvm-project/pull/111717