[llvm] [GlobalISel][AArch64] Legalize G_ADD, G_SUB, G_AND, G_OR, and G_XOR for SVE (PR #110561)

[Thorsten Schütt via llvm-commits]

tschuett wrote:

I have ARM DDI 0487K.a. It lists under SVE integer arithmetic:
```
MUL Multiply by immediate MUL (immediate)
Multiply vectors MUL (vectors, predicated)
MUL (vectors, unpredicated)
```
but the unpredicated is actually SVE2 but listed in the SVE section. 

And `MUL_ZZZ` was not imported. Everything works out of the box. I didn't dare to try `ret` but every else seems to work so fare.

Thanks for taking a look!

https://github.com/llvm/llvm-project/pull/110561