[llvm] [GlobalISel][AArch64] Legalize G_ADD, G_SUB, G_AND, G_OR, and G_XOR for SVE (PR #110561)

[David Green via llvm-commits]

Thorsten =?utf-8?q?Schütt?= <schuett at gmail.com>
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In-Reply-To: <llvm.org/llvm/llvm-project/pull/110561 at github.com>


davemgreen wrote:

For the SVE issue you are seeing - some instructions in SVE are "unpredicated", many require a predicate even if it is an all-on predicate vector. mul I believe is one where there is an predicated +sve instruction, and an unpredicated +sve2 version. SDAG will convert them into MUL_PRED, but that has obvious downsides.

Do you mind if we have a first patch that just gets the arg-passing basics out of the way first, and start adding instruction support separately? Or does that all work already and all of this is for instruction support? We should be able to add tests that pass in values and store them, or load values and return them. I feel we need to make sure SVE is decently designed. I suppose that without any other suggestions we can follow how SDAG behaves.

https://github.com/llvm/llvm-project/pull/110561