[llvm] [RISCV][ISel] Allow emitting `addiw` with u32simm12 rhs (PR #111116)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 4 18:23:35 PDT 2024
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/111116
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