[llvm] [RISCV][GISEL] instruction-select vmclr (PR #110782)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 4 06:19:54 PDT 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/110782
>From 0222bc2a55bec05a7da65a839723b5187b9a4b28 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 1 Oct 2024 19:14:34 -0700
Subject: [PATCH 01/10] [RISCV][GISEL] instruction-select vmclr
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 22 ++++
llvm/lib/Target/RISCV/RISCVGISel.td | 5 +
.../instruction-select/rvv/vmclr-rv32.mir | 124 ++++++++++++++++++
.../instruction-select/rvv/vmclr-rv64.mir | 124 ++++++++++++++++++
4 files changed, 275 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4c2fcd38bd35ac..73707e4c4a4190 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -100,6 +100,8 @@ class RISCVInstructionSelector : public InstructionSelector {
return selectSHXADD_UWOp(Root, ShAmt);
}
+ ComplexRendererFns selectVLOp(MachineOperand &Root) const;
+
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -376,6 +378,26 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
return std::nullopt;
}
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
+ MachineRegisterInfo &MRI =
+ Root.getParent()->getParent()->getParent()->getRegInfo();
+ assert(Root.isReg() && "Expected operand to be a Register");
+ MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
+
+ if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT &&
+ RootDef->getOperand(1).getCImm()->getSExtValue() == RISCV::VLMaxSentinel)
+ // If the operand is a G_CONSTANT with value VLMaxSentinel, convert it
+ // to an immediate with value VLMaxSentinel. This is recognized specially by
+ // the vsetvli insertion pass.
+ return {
+ {[=](MachineInstrBuilder &MIB) { MIB.addImm(RISCV::VLMaxSentinel); }}};
+
+ // FIXME: Implement non-VLMAX case. ISEL will fail gracefully by returning
+ // like this for now.
+ return std::nullopt;
+}
+
InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
if (!Root.isReg())
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index a65577b9cacdae..2b14dfc447fdc7 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -50,6 +50,11 @@ def GIAddrRegImm :
GIComplexOperandMatcher<s32, "selectAddrRegImm">,
GIComplexPatternEquiv<AddrRegImm>;
+def GIVLOpS32 : GIComplexOperandMatcher<s32, "selectVLOp">,
+ GIComplexPatternEquiv<VLOp>;
+def GIVLOpS64 : GIComplexOperandMatcher<s64, "selectVLOp">,
+ GIComplexPatternEquiv<VLOp>;
+
// Convert from i32 immediate to i64 target immediate to make SelectionDAG type
// checking happy so we can use ADDIW which expects an XLen immediate.
def as_i64imm : SDNodeXForm<imm, [{
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
new file mode 100644
index 00000000000000..1ef1312cc17c0e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
@@ -0,0 +1,124 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: splat_zero_nxv1i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv1i1
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv2i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv2i1
+ ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 2 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv4i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv4i1
+ ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 4 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv8i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv8i1
+ ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 8 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv16i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv16i1
+ ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 16 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv32i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv32i1
+ ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 32 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv64i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv64i1
+ ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 64 x s1>)
+ PseudoRET implicit $v0
+
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
new file mode 100644
index 00000000000000..b7541cd4e96fb4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
@@ -0,0 +1,124 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: splat_zero_nxv1i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv1i1
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv2i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv2i1
+ ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 2 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv4i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv4i1
+ ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 4 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv8i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv8i1
+ ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 8 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv16i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv16i1
+ ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 16 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv32i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv32i1
+ ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 32 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv64i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv64i1
+ ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 64 x s1>)
+ PseudoRET implicit $v0
+
+...
+
>From e31dc4a3277f8752d76b06ce7dfa91cdef52df1f Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 1 Oct 2024 19:46:54 -0700
Subject: [PATCH 02/10] fixup! demonstrate the functionality supported in
selectVLOp
---
.../rvv/fail-select-vl-badnegative.mir | 17 +++++++++++++++++
.../rvv/fail-select-vl-nonconst.mir | 19 +++++++++++++++++++
.../rvv/fail-select-vl-nonzero.mir | 19 +++++++++++++++++++
.../rvv/fail-select-vl-zero.mir | 18 ++++++++++++++++++
4 files changed, 73 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir
new file mode 100644
index 00000000000000..f71c0aab9c05ef
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir
@@ -0,0 +1,17 @@
+# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
+
+---
+# CHECK: LLVM ERROR: cannot select:
+name: bad_negative_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ %0:gprb(s32) = G_CONSTANT i32 -2
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
new file mode 100644
index 00000000000000..88d301f752a7dc
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
@@ -0,0 +1,19 @@
+# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
+
+# FIXME: This should be supported in the future
+---
+name: not_implemented_vl_nonconst
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+ %0:gprb(s32) = COPY $x10
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+# CHECK: LLVM ERROR: cannot select
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
new file mode 100644
index 00000000000000..f12a800a4a2eef
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
@@ -0,0 +1,19 @@
+# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
+
+# FIXME: This should be supported in the future
+---
+name: not_implemented_vl_nonzero
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ %0:gprb(s32) = G_CONSTANT i32 1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+# CHECK: LLVM ERROR: cannot select
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
new file mode 100644
index 00000000000000..9338e4fb32e3a2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
@@ -0,0 +1,18 @@
+# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
+
+# FIXME: This should be supported in the future
+---
+# CHECK: LLVM ERROR: cannot select
+name: not_implemented_vl0
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ %0:gprb(s32) = G_CONSTANT i32 0
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+...
>From d738b68475e744a6bcc248ec9fbb96b4abcd9077 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 1 Oct 2024 20:47:18 -0700
Subject: [PATCH 03/10] fixup! implement non-VLMAX cases in selectVLOp
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 26 ++++---
.../rvv/fail-select-vl-nonconst.mir | 19 -----
.../rvv/fail-select-vl-nonzero.mir | 19 -----
.../rvv/fail-select-vl-zero.mir | 18 -----
.../instruction-select/rvv/select-vlop.mir | 70 +++++++++++++++++++
5 files changed, 85 insertions(+), 67 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 73707e4c4a4190..5da1a6f489c467 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -385,17 +385,21 @@ RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
assert(Root.isReg() && "Expected operand to be a Register");
MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
- if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT &&
- RootDef->getOperand(1).getCImm()->getSExtValue() == RISCV::VLMaxSentinel)
- // If the operand is a G_CONSTANT with value VLMaxSentinel, convert it
- // to an immediate with value VLMaxSentinel. This is recognized specially by
- // the vsetvli insertion pass.
- return {
- {[=](MachineInstrBuilder &MIB) { MIB.addImm(RISCV::VLMaxSentinel); }}};
-
- // FIXME: Implement non-VLMAX case. ISEL will fail gracefully by returning
- // like this for now.
- return std::nullopt;
+ if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT) {
+ auto C = RootDef->getOperand(1).getCImm();
+ if (C->getSExtValue() == RISCV::VLMaxSentinel || C->getValue().isAllOnes())
+ // If the operand is a G_CONSTANT with value VLMaxSentinel or all ones,
+ // convert it to an immediate with value VLMaxSentinel. This is recognized
+ // specially by the vsetvli insertion pass.
+ return {{[=](MachineInstrBuilder &MIB) {
+ MIB.addImm(RISCV::VLMaxSentinel);
+ }}};
+
+ if (isUInt<5>(C->getZExtValue()))
+ return {
+ {[=](MachineInstrBuilder &MIB) { MIB.addImm(C->getZExtValue()); }}};
+ }
+ return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }}};
}
InstructionSelector::ComplexRendererFns
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
deleted file mode 100644
index 88d301f752a7dc..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
+++ /dev/null
@@ -1,19 +0,0 @@
-# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
-# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
-
-# FIXME: This should be supported in the future
----
-name: not_implemented_vl_nonconst
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1:
- liveins: $x10
- %0:gprb(s32) = COPY $x10
- %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
- $v0 = COPY %1(<vscale x 1 x s1>)
- PseudoRET implicit $v0
-
-# CHECK: LLVM ERROR: cannot select
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
deleted file mode 100644
index f12a800a4a2eef..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
+++ /dev/null
@@ -1,19 +0,0 @@
-# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
-# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
-
-# FIXME: This should be supported in the future
----
-name: not_implemented_vl_nonzero
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1:
- %0:gprb(s32) = G_CONSTANT i32 1
- %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
- $v0 = COPY %1(<vscale x 1 x s1>)
- PseudoRET implicit $v0
-
-# CHECK: LLVM ERROR: cannot select
-...
-
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
deleted file mode 100644
index 9338e4fb32e3a2..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
+++ /dev/null
@@ -1,18 +0,0 @@
-# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
-# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
-
-# FIXME: This should be supported in the future
----
-# CHECK: LLVM ERROR: cannot select
-name: not_implemented_vl0
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1:
- %0:gprb(s32) = G_CONSTANT i32 0
- %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
- $v0 = COPY %1(<vscale x 1 x s1>)
- PseudoRET implicit $v0
-
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir
new file mode 100644
index 00000000000000..d43195c8b00968
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir
@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+name: negative_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ %0:gprb(s32) = G_CONSTANT i32 -2
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+---
+name: nonconst_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+ ; CHECK-LABEL: name: nonconst_vl
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = COPY $x10
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
+---
+name: nonzero_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: nonzero_vl
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
+---
+name: zero_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: zero_vl
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 0
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
>From a10c060a8c9f4577cf2ab4db866f4a24f71e327d Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 1 Oct 2024 20:52:51 -0700
Subject: [PATCH 04/10] fixup! remove check for sentinel
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 5da1a6f489c467..d7b06a43218d7e 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -387,10 +387,10 @@ RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT) {
auto C = RootDef->getOperand(1).getCImm();
- if (C->getSExtValue() == RISCV::VLMaxSentinel || C->getValue().isAllOnes())
- // If the operand is a G_CONSTANT with value VLMaxSentinel or all ones,
- // convert it to an immediate with value VLMaxSentinel. This is recognized
- // specially by the vsetvli insertion pass.
+ if (C->getValue().isAllOnes())
+ // If the operand is a G_CONSTANT with value of all ones it is larger than
+ // VLMAX. We convert it to an immediate with value VLMaxSentinel. This is
+ // recognized specially by the vsetvli insertion pass.
return {{[=](MachineInstrBuilder &MIB) {
MIB.addImm(RISCV::VLMaxSentinel);
}}};
>From fdd45f1b3100fe345a086aed3a2e483130a99960 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 1 Oct 2024 21:03:36 -0700
Subject: [PATCH 05/10] fixup! add end to end
---
.../RISCV/GlobalISel/rvv/splat-vector.ll | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/rvv/splat-vector.ll
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/splat-vector.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/splat-vector.ll
new file mode 100644
index 00000000000000..4e58c4dcec2d85
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/splat-vector.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh -global-isel \
+; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -global-isel \
+; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
+
+define <vscale x 1 x i1> @splat_zero_nxv1i1() {
+; CHECK-LABEL: splat_zero_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 1 x i1> zeroinitializer
+}
+
+define <vscale x 2 x i1> @splat_zero_nxv2i1() {
+; CHECK-LABEL: splat_zero_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 2 x i1> zeroinitializer
+}
+
+define <vscale x 4 x i1> @splat_zero_nxv4i1() {
+; CHECK-LABEL: splat_zero_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 4 x i1> zeroinitializer
+}
+
+define <vscale x 8 x i1> @splat_zero_nxv8i1() {
+; CHECK-LABEL: splat_zero_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 8 x i1> zeroinitializer
+}
+
+define <vscale x 16 x i1> @splat_zero_nxv16i1() {
+; CHECK-LABEL: splat_zero_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 16 x i1> zeroinitializer
+}
+
+define <vscale x 32 x i1> @splat_zero_nxv32i1() {
+; CHECK-LABEL: splat_zero_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 32 x i1> zeroinitializer
+}
+
+define <vscale x 64 x i1> @splat_zero_nxv64i1() {
+; CHECK-LABEL: splat_zero_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 64 x i1> zeroinitializer
+}
+
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}
+; RV64: {{.*}}
>From 1fa0f30d59bc01f25cbc6ecc97b8b40db773bb00 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 2 Oct 2024 09:33:49 -0700
Subject: [PATCH 06/10] fixup! respond to review
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVGISel.td | 4 ++--
.../rvv/fail-select-vl-badnegative.mir | 17 -----------------
.../rvv/{select-vlop.mir => render-vlop.mir} | 6 ++++++
4 files changed, 10 insertions(+), 21 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir
rename llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/{select-vlop.mir => render-vlop.mir} (88%)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index d7b06a43218d7e..b1c663d9f13c25 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -100,7 +100,7 @@ class RISCVInstructionSelector : public InstructionSelector {
return selectSHXADD_UWOp(Root, ShAmt);
}
- ComplexRendererFns selectVLOp(MachineOperand &Root) const;
+ ComplexRendererFns renderVLOp(MachineOperand &Root) const;
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
@@ -379,7 +379,7 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
}
InstructionSelector::ComplexRendererFns
-RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
+RISCVInstructionSelector::renderVLOp(MachineOperand &Root) const {
MachineRegisterInfo &MRI =
Root.getParent()->getParent()->getParent()->getRegInfo();
assert(Root.isReg() && "Expected operand to be a Register");
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 2b14dfc447fdc7..d7266cfd03919a 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -50,9 +50,9 @@ def GIAddrRegImm :
GIComplexOperandMatcher<s32, "selectAddrRegImm">,
GIComplexPatternEquiv<AddrRegImm>;
-def GIVLOpS32 : GIComplexOperandMatcher<s32, "selectVLOp">,
+def GIVLOpS32 : GIComplexOperandMatcher<s32, "renderVLOp">,
GIComplexPatternEquiv<VLOp>;
-def GIVLOpS64 : GIComplexOperandMatcher<s64, "selectVLOp">,
+def GIVLOpS64 : GIComplexOperandMatcher<s64, "renderVLOp">,
GIComplexPatternEquiv<VLOp>;
// Convert from i32 immediate to i64 target immediate to make SelectionDAG type
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir
deleted file mode 100644
index f71c0aab9c05ef..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir
+++ /dev/null
@@ -1,17 +0,0 @@
-# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
-# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
-
----
-# CHECK: LLVM ERROR: cannot select:
-name: bad_negative_vl
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1:
- %0:gprb(s32) = G_CONSTANT i32 -2
- %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
- $v0 = COPY %1(<vscale x 1 x s1>)
- PseudoRET implicit $v0
-...
-
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop.mir
similarity index 88%
rename from llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir
rename to llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop.mir
index d43195c8b00968..5600e351aa3987 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop.mir
@@ -2,12 +2,18 @@
# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+---
name: negative_vl
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
+ ; CHECK-LABEL: name: negative_vl
+ ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
%0:gprb(s32) = G_CONSTANT i32 -2
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
$v0 = COPY %1(<vscale x 1 x s1>)
>From ade6f35f6d364cb13377a3fca7f7efe8bf4c1179 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 2 Oct 2024 09:35:57 -0700
Subject: [PATCH 07/10] fixup! show render-vlop works for rv32 and rv64
---
.../{render-vlop.mir => render-vlop-rv32.mir} | 0
.../rvv/render-vlop-rv64.mir | 76 +++++++++++++++++++
2 files changed, 76 insertions(+)
rename llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/{render-vlop.mir => render-vlop-rv32.mir} (100%)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir
similarity index 100%
rename from llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop.mir
rename to llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir
new file mode 100644
index 00000000000000..c2c0ed72be7b7c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir
@@ -0,0 +1,76 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: negative_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: negative_vl
+ ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -2
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+---
+name: nonconst_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+ ; CHECK-LABEL: name: nonconst_vl
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = COPY $x10
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
+---
+name: nonzero_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: nonzero_vl
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
+---
+name: zero_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: zero_vl
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 0
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
>From 388dfb02e41039911b2d6f6b865a8c493f4a23c4 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 2 Oct 2024 09:47:38 -0700
Subject: [PATCH 08/10] fixup! remove multiple render defs
---
llvm/lib/Target/RISCV/RISCVGISel.td | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index d7266cfd03919a..0656928ca41f83 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -50,10 +50,13 @@ def GIAddrRegImm :
GIComplexOperandMatcher<s32, "selectAddrRegImm">,
GIComplexPatternEquiv<AddrRegImm>;
-def GIVLOpS32 : GIComplexOperandMatcher<s32, "renderVLOp">,
- GIComplexPatternEquiv<VLOp>;
-def GIVLOpS64 : GIComplexOperandMatcher<s64, "renderVLOp">,
- GIComplexPatternEquiv<VLOp>;
+// FIXME: This is labelled as handling 's32', however the ComplexPattern it
+// refers to handles both i32 and i64 based on the HwMode. Currently this LLT
+// parameter appears to be ignored so this pattern works for both, however we
+// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
+// here.
+def GIVLOp : GIComplexOperandMatcher<s32, "renderVLOp">,
+ GIComplexPatternEquiv<VLOp>;
// Convert from i32 immediate to i64 target immediate to make SelectionDAG type
// checking happy so we can use ADDIW which expects an XLen immediate.
>From 4187c4768a75571bcd1b32b56173ba7d83eda22c Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 3 Oct 2024 11:35:51 -0700
Subject: [PATCH 09/10] fixup! improve formatting
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index b1c663d9f13c25..294c12fdbf684d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -395,9 +395,10 @@ RISCVInstructionSelector::renderVLOp(MachineOperand &Root) const {
MIB.addImm(RISCV::VLMaxSentinel);
}}};
- if (isUInt<5>(C->getZExtValue()))
- return {
- {[=](MachineInstrBuilder &MIB) { MIB.addImm(C->getZExtValue()); }}};
+ if (isUInt<5>(C->getZExtValue())) {
+ uint64_t ZExtC = C->getZExtValue();
+ return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(ZExtC); }}};
+ }
}
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }}};
}
>From 5a77b97038b90fe4be63c9134e4acb37162bd8f4 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Fri, 4 Oct 2024 06:17:24 -0700
Subject: [PATCH 10/10] fixup! use MRI from member variable
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 294c12fdbf684d..cfe8644b892298 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -380,10 +380,8 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::renderVLOp(MachineOperand &Root) const {
- MachineRegisterInfo &MRI =
- Root.getParent()->getParent()->getParent()->getRegInfo();
assert(Root.isReg() && "Expected operand to be a Register");
- MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
+ MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT) {
auto C = RootDef->getOperand(1).getCImm();
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