[llvm] [RISCV][GISEL] instruction-select vmclr (PR #110782)

[Michael Maitland via llvm-commits]

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@@ -379,6 +381,30 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
   return std::nullopt;
 }
 
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::renderVLOp(MachineOperand &Root) const {
+  MachineRegisterInfo &MRI =
+      Root.getParent()->getParent()->getParent()->getRegInfo();
+  assert(Root.isReg() && "Expected operand to be a Register");
+  MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
+
+  if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT) {
+    auto C = RootDef->getOperand(1).getCImm();
+    if (C->getValue().isAllOnes())
+      // If the operand is a G_CONSTANT with value of all ones it is larger than
+      // VLMAX. We convert it to an immediate with value VLMaxSentinel. This is
+      // recognized specially by the vsetvli insertion pass.
+      return {{[=](MachineInstrBuilder &MIB) {
+        MIB.addImm(RISCV::VLMaxSentinel);
+      }}};
+
+    if (isUInt<5>(C->getZExtValue()))
+      return {
+          {[=](MachineInstrBuilder &MIB) { MIB.addImm(C->getZExtValue()); }}};
+  }
+  return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }}};
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michaelmaitland wrote:

addressed.

https://github.com/llvm/llvm-project/pull/110782