[llvm] [RISCV][DAGCombine] Combine `sext_inreg (shl X, Y), i32` into `sllw X, Y` (PR #111101)

Yingwei Zheng via llvm-commits llvm-commits at lists.llvm.org
Fri Oct 4 01:03:15 PDT 2024

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https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/111101

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