[llvm] [RISCV][GISEL] instruction-select vmclr (PR #110782)

[Matt Arsenault via llvm-commits]

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@@ -379,6 +381,30 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
   return std::nullopt;
 }
 
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::renderVLOp(MachineOperand &Root) const {
+  MachineRegisterInfo &MRI =
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arsenm wrote:

Yes 

https://github.com/llvm/llvm-project/pull/110782