[llvm] [feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv (PR #109914)

[Craig Topper via llvm-commits]

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@@ -230,6 +236,44 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
     return false;
   }
 
+  bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+                      uint64_t &Target) const override {
+    switch(Inst.getOpcode()) {
+      default:
+        return false;
+      case RISCV::ADDI:
+      case RISCV::ADDIW: {
+        if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+          Target  = *TargetRegState + Inst.getOperand(2).getImm();
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topperc wrote:

ADDIW adds bit 31:0 of both inputs, calculates a 32 bit result then sign extends that to 64 bits. Bits 63:32 of the inputs are discarded and don't affect the result. This is different than adding 2 int64_t values together.

https://github.com/llvm/llvm-project/pull/109914