[llvm] [feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv (PR #109914)

[Arjun Patel via llvm-commits]

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@@ -230,6 +236,44 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
     return false;
   }
 
+  bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+                      uint64_t &Target) const override {
+    switch(Inst.getOpcode()) {
+      default:
+        return false;
+      case RISCV::ADDI:
+      case RISCV::ADDIW: {
+        if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+          Target  = *TargetRegState + Inst.getOperand(2).getImm();
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arjunUpatel wrote:

I am still a bit confused by this feedback, mainly because to my understanding, the sign extension of the result is being handled by the fact that the values are loaded in memory already sign extended to 64 bits along with 2s complement addition preserving the sign extension over arithmetic manipulation.

Here is my understanding so far:
1. A signed value, extended to 64 bits, is loaded into `*TargetRegState` by either AUIPC or LUI
2. The immediate value, also already sign extended to 64 bits, is added to `*TargetRegState`
3. 2s complement addition is carried out. The sum will stay sign extended to 64 bits as per 2s complement

Is this correct or am I missing something?



https://github.com/llvm/llvm-project/pull/109914