[llvm] c38b5c8 - [LoongArch] Use MCRegister. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-09-29T13:22:28-07:00
New Revision: c38b5c81bbd44bffd61831630ef434956608b6a5

URL: https://github.com/llvm/llvm-project/commit/c38b5c81bbd44bffd61831630ef434956608b6a5
DIFF: https://github.com/llvm/llvm-project/commit/c38b5c81bbd44bffd61831630ef434956608b6a5.diff

LOG: [LoongArch] Use MCRegister. NFC

Added: 
    

Modified: 
    llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
index 57c42024b4d2b2..e3abb7eecc32b1 100644
--- a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+++ b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
@@ -559,10 +559,10 @@ class LoongArchOperand : public MCParsedAsmOperand {
     return Op;
   }
 
-  static std::unique_ptr<LoongArchOperand> createReg(unsigned RegNo, SMLoc S,
+  static std::unique_ptr<LoongArchOperand> createReg(MCRegister Reg, SMLoc S,
                                                      SMLoc E) {
     auto Op = std::make_unique<LoongArchOperand>(KindTy::Register);
-    Op->Reg.RegNum = RegNo;
+    Op->Reg.RegNum = Reg;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
@@ -1424,9 +1424,9 @@ unsigned LoongArchAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   switch (Opc) {
   default:
     if (Opc >= LoongArch::AMADD_D && Opc <= LoongArch::AMXOR_W) {
-      unsigned Rd = Inst.getOperand(0).getReg();
-      unsigned Rk = Inst.getOperand(1).getReg();
-      unsigned Rj = Inst.getOperand(2).getReg();
+      MCRegister Rd = Inst.getOperand(0).getReg();
+      MCRegister Rk = Inst.getOperand(1).getReg();
+      MCRegister Rj = Inst.getOperand(2).getReg();
       if ((Rd == Rk || Rd == Rj) && Rd != LoongArch::R0)
         return Match_RequiresAMORdDifferRkRj;
     }
@@ -1435,7 +1435,7 @@ unsigned LoongArchAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   case LoongArch::PseudoLA_TLS_DESC_ABS_LARGE:
   case LoongArch::PseudoLA_TLS_DESC_PC:
   case LoongArch::PseudoLA_TLS_DESC_PC_LARGE: {
-    unsigned Rd = Inst.getOperand(0).getReg();
+    MCRegister Rd = Inst.getOperand(0).getReg();
     if (Rd != LoongArch::R4)
       return Match_RequiresLAORdR4;
     break;
@@ -1445,15 +1445,15 @@ unsigned LoongArchAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   case LoongArch::PseudoLA_TLS_IE_LARGE:
   case LoongArch::PseudoLA_TLS_LD_LARGE:
   case LoongArch::PseudoLA_TLS_GD_LARGE: {
-    unsigned Rd = Inst.getOperand(0).getReg();
-    unsigned Rj = Inst.getOperand(1).getReg();
+    MCRegister Rd = Inst.getOperand(0).getReg();
+    MCRegister Rj = Inst.getOperand(1).getReg();
     if (Rd == Rj)
       return Match_RequiresLAORdDifferRj;
     break;
   }
   case LoongArch::CSRXCHG:
   case LoongArch::GCSRXCHG: {
-    unsigned Rj = Inst.getOperand(2).getReg();
+    MCRegister Rj = Inst.getOperand(2).getReg();
     if (Rj == LoongArch::R0 || Rj == LoongArch::R1)
       return Match_RequiresOpnd2NotR0R1;
     return Match_Success;