[llvm] [RISCV] Add 32 bit GPR sub-register for Zfinx. (PR #108336)

[Yingwei Zheng via llvm-commits]

================
@@ -364,11 +401,17 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
     }
   }
 
+  if ((ValVT == MVT::f32 && Subtarget.hasStdExtZfinx())) {
----------------
dtcxzyw wrote:

```suggestion
  if (ValVT == MVT::f32 && Subtarget.hasStdExtZfinx()) {
```

https://github.com/llvm/llvm-project/pull/108336