[llvm] 9f255d8 - [AArch64][GlobalISel] Lower fp16 abs and neg without fullfp16. (#110096)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 26 23:44:01 PDT 2024
Author: David Green
Date: 2024-09-27T07:43:58+01:00
New Revision: 9f255d863f31f3d3c434f662dc9e2255ef54407c
URL: https://github.com/llvm/llvm-project/commit/9f255d863f31f3d3c434f662dc9e2255ef54407c
DIFF: https://github.com/llvm/llvm-project/commit/9f255d863f31f3d3c434f662dc9e2255ef54407c.diff
LOG: [AArch64][GlobalISel] Lower fp16 abs and neg without fullfp16. (#110096)
This changes the existing promote logic to lower, so that it can use
normal integer operations. A minor change was needed to fneg lower code
to handle vectors.
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
llvm/test/CodeGen/AArch64/f16-instructions.ll
llvm/test/CodeGen/AArch64/fabs.ll
llvm/test/CodeGen/AArch64/fneg.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index c3b6b3033cf5c4..2fb2d104f1ce34 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -4051,12 +4051,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
auto [Res, SubByReg] = MI.getFirst2Regs();
LLT Ty = MRI.getType(Res);
- // TODO: Handle vector types once we are able to
- // represent them.
- if (Ty.isVector())
- return UnableToLegalize;
- auto SignMask =
- MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits()));
+ auto SignMask = MIRBuilder.buildConstant(
+ Ty, APInt::getSignMask(Ty.getScalarSizeInBits()));
MIRBuilder.buildXor(Res, SubByReg, SignMask);
MI.eraseFromParent();
return Legalized;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 6cb181011f8f67..51aeee023f2e34 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -268,11 +268,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
})
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.lowerIf(scalarOrEltWiderThan(0, 64))
- .minScalarOrElt(0, MinFPScalar)
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
- .moreElementsToNextPow2(0);
+ .moreElementsToNextPow2(0)
+ .lowerFor({s16, v4s16, v8s16});
getActionDefinitionsBuilder(G_FREM)
.libcallFor({s32, s64})
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
index 438b347fcbcabe..42538d58c87bf2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
@@ -150,9 +150,10 @@ body: |
; NO-FP16: liveins: $h0
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %x:_(s16) = COPY $h0
- ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
- ; NO-FP16-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FPEXT]]
- ; NO-FP16-NEXT: %op:_(s16) = G_FPTRUNC [[FNEG]](s32)
+ ; NO-FP16-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %x(s16)
+ ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; NO-FP16-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ANYEXT]], [[C]]
+ ; NO-FP16-NEXT: %op:_(s16) = G_TRUNC [[XOR]](s32)
; NO-FP16-NEXT: $h0 = COPY %op(s16)
; NO-FP16-NEXT: RET_ReallyLR implicit $h0
;
diff --git a/llvm/test/CodeGen/AArch64/f16-instructions.ll b/llvm/test/CodeGen/AArch64/f16-instructions.ll
index d8a17b40587106..e058c83f274f14 100644
--- a/llvm/test/CodeGen/AArch64/f16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/f16-instructions.ll
@@ -1392,26 +1392,19 @@ define half @test_fma(half %a, half %b, half %c) #0 {
}
define half @test_fabs(half %a) #0 {
-; CHECK-CVT-SD-LABEL: test_fabs:
-; CHECK-CVT-SD: // %bb.0:
-; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 def $s0
-; CHECK-CVT-SD-NEXT: fmov w8, s0
-; CHECK-CVT-SD-NEXT: and w8, w8, #0x7fff
-; CHECK-CVT-SD-NEXT: fmov s0, w8
-; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $s0
-; CHECK-CVT-SD-NEXT: ret
+; CHECK-CVT-LABEL: test_fabs:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0
+; CHECK-CVT-NEXT: fmov w8, s0
+; CHECK-CVT-NEXT: and w8, w8, #0x7fff
+; CHECK-CVT-NEXT: fmov s0, w8
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: test_fabs:
; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fabs h0, h0
; CHECK-FP16-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: test_fabs:
-; CHECK-CVT-GI: // %bb.0:
-; CHECK-CVT-GI-NEXT: fcvt s0, h0
-; CHECK-CVT-GI-NEXT: fabs s0, s0
-; CHECK-CVT-GI-NEXT: fcvt h0, s0
-; CHECK-CVT-GI-NEXT: ret
%r = call half @llvm.fabs.f16(half %a)
ret half %r
}
diff --git a/llvm/test/CodeGen/AArch64/fabs.ll b/llvm/test/CodeGen/AArch64/fabs.ll
index e19e2ead11f4d0..43e90070736345 100644
--- a/llvm/test/CodeGen/AArch64/fabs.ll
+++ b/llvm/test/CodeGen/AArch64/fabs.ll
@@ -41,9 +41,11 @@ define half @fabs_f16(half %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: fcvt s0, h0
-; CHECK-GI-NOFP16-NEXT: fabs s0, s0
-; CHECK-GI-NOFP16-NEXT: fcvt h0, s0
+; CHECK-GI-NOFP16-NEXT: // kill: def $h0 killed $h0 def $s0
+; CHECK-GI-NOFP16-NEXT: fmov w8, s0
+; CHECK-GI-NOFP16-NEXT: and w8, w8, #0x7fff
+; CHECK-GI-NOFP16-NEXT: fmov s0, w8
+; CHECK-GI-NOFP16-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_f16:
@@ -160,22 +162,8 @@ define <7 x half> @fabs_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov v2.h[0], v0.h[4]
-; CHECK-GI-NOFP16-NEXT: fabs v1.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[1]
-; CHECK-GI-NOFP16-NEXT: fabs v2.4s, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v1.h[2]
-; CHECK-GI-NOFP16-NEXT: fcvtn v2.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v1.h[3]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[4], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[1]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v2.h[2]
+; CHECK-GI-NOFP16-NEXT: mvni v1.8h, #128, lsl #8
+; CHECK-GI-NOFP16-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v7f16:
@@ -200,9 +188,8 @@ define <4 x half> @fabs_v4f16(<4 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v4f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fabs v0.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NOFP16-NEXT: mvni v1.4h, #128, lsl #8
+; CHECK-GI-NOFP16-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v4f16:
@@ -227,12 +214,8 @@ define <8 x half> @fabs_v8f16(<8 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v8f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-NOFP16-NEXT: fabs v1.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: fabs v2.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn2 v0.8h, v2.4s
+; CHECK-GI-NOFP16-NEXT: mvni v1.8h, #128, lsl #8
+; CHECK-GI-NOFP16-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v8f16:
@@ -259,18 +242,9 @@ define <16 x half> @fabs_v16f16(<16 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v16f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h
-; CHECK-GI-NOFP16-NEXT: fabs v2.4s, v2.4s
-; CHECK-GI-NOFP16-NEXT: fabs v3.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: fabs v4.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: fabs v5.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v3.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn2 v0.8h, v4.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn2 v1.8h, v5.4s
+; CHECK-GI-NOFP16-NEXT: mvni v2.8h, #128, lsl #8
+; CHECK-GI-NOFP16-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NOFP16-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v16f16:
diff --git a/llvm/test/CodeGen/AArch64/fneg.ll b/llvm/test/CodeGen/AArch64/fneg.ll
index a0e9edff733e09..de2671afe60ab7 100644
--- a/llvm/test/CodeGen/AArch64/fneg.ll
+++ b/llvm/test/CodeGen/AArch64/fneg.ll
@@ -41,9 +41,11 @@ define half @fabs_f16(half %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: fcvt s0, h0
-; CHECK-GI-NOFP16-NEXT: fneg s0, s0
-; CHECK-GI-NOFP16-NEXT: fcvt h0, s0
+; CHECK-GI-NOFP16-NEXT: // kill: def $h0 killed $h0 def $s0
+; CHECK-GI-NOFP16-NEXT: fmov w8, s0
+; CHECK-GI-NOFP16-NEXT: eor w8, w8, #0xffff8000
+; CHECK-GI-NOFP16-NEXT: fmov s0, w8
+; CHECK-GI-NOFP16-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_f16:
@@ -161,22 +163,8 @@ define <7 x half> @fabs_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov v2.h[0], v0.h[4]
-; CHECK-GI-NOFP16-NEXT: fneg v1.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[1]
-; CHECK-GI-NOFP16-NEXT: fneg v2.4s, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v1.h[2]
-; CHECK-GI-NOFP16-NEXT: fcvtn v2.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v1.h[3]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[4], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[1]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v2.h[2]
+; CHECK-GI-NOFP16-NEXT: movi v1.8h, #128, lsl #8
+; CHECK-GI-NOFP16-NEXT: eor v0.16b, v0.16b, v1.16b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v7f16:
@@ -202,9 +190,8 @@ define <4 x half> @fabs_v4f16(<4 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v4f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fneg v0.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NOFP16-NEXT: movi v1.4h, #128, lsl #8
+; CHECK-GI-NOFP16-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v4f16:
@@ -230,12 +217,8 @@ define <8 x half> @fabs_v8f16(<8 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v8f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-NOFP16-NEXT: fneg v1.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: fneg v2.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn2 v0.8h, v2.4s
+; CHECK-GI-NOFP16-NEXT: movi v1.8h, #128, lsl #8
+; CHECK-GI-NOFP16-NEXT: eor v0.16b, v0.16b, v1.16b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v8f16:
@@ -263,18 +246,9 @@ define <16 x half> @fabs_v16f16(<16 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v16f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h
-; CHECK-GI-NOFP16-NEXT: fneg v2.4s, v2.4s
-; CHECK-GI-NOFP16-NEXT: fneg v3.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: fneg v4.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: fneg v5.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v3.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn2 v0.8h, v4.4s
-; CHECK-GI-NOFP16-NEXT: fcvtn2 v1.8h, v5.4s
+; CHECK-GI-NOFP16-NEXT: movi v2.8h, #128, lsl #8
+; CHECK-GI-NOFP16-NEXT: eor v0.16b, v0.16b, v2.16b
+; CHECK-GI-NOFP16-NEXT: eor v1.16b, v1.16b, v2.16b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v16f16:
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