[llvm] [RISCV][MC] Support Assembling 48- and 64-bit Instructions (PR #110022)
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Thu Sep 26 06:54:50 PDT 2024
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git-clang-format --diff 0f521931b85e6b5f798af357cf32a7ae782a848d 306c1bdbc59895143d4fa0806d7166d7ed3626b6 --extensions cpp,h -- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
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diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index f42aac2816..fe38e04bc5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3161,22 +3161,26 @@ bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) {
return true;
if (*Length == 0 || (*Length % 2) != 0)
- return Error(ErrorLoc, "instruction lengths must be a non-zero multiple of two");
+ return Error(ErrorLoc,
+ "instruction lengths must be a non-zero multiple of two");
// TODO: Support Instructions > 64 bits.
if (Length > 8)
return Error(ErrorLoc,
- "instruction lengths over 64 bits are not supported");
+ "instruction lengths over 64 bits are not supported");
}
- // We only derive a length from the encoding for 16- and 32-bit instructions, as
- // the encodings for longer instructions are not frozen in the spec.
+ // We only derive a length from the encoding for 16- and 32-bit
+ // instructions, as the encodings for longer instructions are not frozen in
+ // the spec.
int64_t EncodingDerivedLength = ((Value & 0b11) == 0b11) ? 4 : 2;
if (Length) {
- // Only check the length against the encoding if the length is present and could match
+ // Only check the length against the encoding if the length is present and
+ // could match
if ((*Length <= 4) && (*Length != EncodingDerivedLength))
- return Error(ErrorLoc, "instruction length does not match the encoding");
+ return Error(ErrorLoc,
+ "instruction length does not match the encoding");
if (!isUIntN(*Length * 8, Value))
return Error(ErrorLoc, "encoding value does not fit into instruction");
@@ -3193,7 +3197,6 @@ bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) {
return true;
}
-
unsigned Opcode;
if (Length) {
switch (*Length) {
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https://github.com/llvm/llvm-project/pull/110022
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