[llvm] MTM: improve operand latency when missing sched info (PR #101389)

[Ramkumar Ramachandra via llvm-commits]

artagnon wrote:

> > > Is this only useful for incomplete targets?
> > 
> > 
> > It is useful when the CPU doesn't have a scheduler descriptor checked into the tree. This happens in the real-world on my X86 box, for instance.
> 
> what x86 are you missing scheduler support for?

I should have been clearer: I think there are scheduler descriptor files for most (if not all) CPUs in the X86 world in the tree, but since my distro's Clang can't know about my hardware, an `-mtune` argument isn't baked in. In the RISC-V world, we only have scheduler descriptor for a few CPUs, including SiFive, in the tree.

https://github.com/llvm/llvm-project/pull/101389