[llvm] MTM: improve operand latency when missing sched info (PR #101389)

[Simon Pilgrim via llvm-commits]

RKSimon wrote:

> > Is this only useful for incomplete targets?
> 
> It is useful when the CPU doesn't have a scheduler descriptor checked into the tree. This happens in the real-world on my X86 box, for instance.

what x86 are you missing scheduler support for?

https://github.com/llvm/llvm-project/pull/101389