[llvm] AArch64: Add FMINNUM_IEEE and FMAXNUM_IEEE support (PR #107855)

[YunQiang Su via llvm-commits]

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@@ -10229,6 +10249,28 @@ SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
   return BitCast(VT, BSP, DAG);
 }
 
+SDValue
+AArch64TargetLowering::LowerFMINIMUMNUM_FMAXIMUMNUM(SDValue Op,
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wzssyqa wrote:

It's due to the limitation of  `narrowInsertExtractVectorBinOp`.

https://github.com/llvm/llvm-project/pull/107855