[llvm] AArch64: Add FMINNUM_IEEE and FMAXNUM_IEEE support (PR #107855)

[YunQiang Su via llvm-commits]

================
@@ -1345,18 +1350,30 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
 
     // AArch64 has implementations of a lot of rounding-like FP operations.
+    // And the same for FMAXNUM_IEEE and FMINNUM_IEEE.
     for (auto Op :
          {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC,
-          ISD::FROUND, ISD::FROUNDEVEN, ISD::STRICT_FFLOOR,
-          ISD::STRICT_FNEARBYINT, ISD::STRICT_FCEIL, ISD::STRICT_FRINT,
-          ISD::STRICT_FTRUNC, ISD::STRICT_FROUND, ISD::STRICT_FROUNDEVEN}) {
+          ISD::FROUND, ISD::FROUNDEVEN, ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE,
+          ISD::STRICT_FFLOOR, ISD::STRICT_FNEARBYINT, ISD::STRICT_FCEIL,
+          ISD::STRICT_FRINT, ISD::STRICT_FTRUNC, ISD::STRICT_FROUND,
+          ISD::STRICT_FROUNDEVEN}) {
       for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64})
         setOperationAction(Op, Ty, Legal);
       if (Subtarget->hasFullFP16())
         for (MVT Ty : {MVT::v4f16, MVT::v8f16})
           setOperationAction(Op, Ty, Legal);
     }
 
+    // In fact TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM works well with
+    // them. While in narrowInsertExtractVectorBinOp, they are expected to be
+    // LegalOrCustom.
----------------
wzssyqa wrote:

In the function `narrowInsertExtractVectorBinOp` of SelectionDAG/DAGCombiner.cpp, if the operation is not Legal or Custom, it refused to split the vector longer than the SIMD unit of CPU.

Aka the IR like
```
define <8 x float> @max_nnan_v8f32(<8 x float> %a, <8 x float> %b) {
entry:
  %c = call nnan <8 x float> @llvm.maximumnum.v8f32(<8 x float> %a, <8 x float> %b)
  ret <8 x float> %c
}
```
will fail to be build with ARM64 NEON. The error msg is like
```
unknown how to split ...
```

https://github.com/llvm/llvm-project/pull/107855