[llvm] [MIPS] Fix failing to legalize load+call with vector of non-p2 intege… (PR #109625)

[via llvm-commits]

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@@ -0,0 +1,30 @@
+; RUN: llc -mtriple=mips-linux-gnu -mcpu=mips32 < %s | FileCheck %s --check-prefix=MIPS32
+
+define void @call_v1i80() {
+; MIPS32-LABEL: call_v1i80:
+; MIPS32:       # %bb.0: # %Entry
+; MIPS32-NEXT:    addiu $sp, $sp, -8
+; MIPS32-NEXT:    .cfi_def_cfa_offset 8
+; MIPS32-NEXT:    sw $ra, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    addiu	$1, $zero, 4
+; MIPS32-NEXT:    lw $1, 0($1)
+; MIPS32-NEXT:    srl $2, $1, 16
+; MIPS32-NEXT:    lw $3, 0($zero)
+; MIPS32-NEXT:    sll $4, $3, 16
+; MIPS32-NEXT:    or $5, $4, $2
+; MIPS32-NEXT:    addiu	$2, $zero, 8
+; MIPS32-NEXT:    lhu $2, 0($2)
+; MIPS32-NEXT:    sll $1, $1, 16
+; MIPS32-NEXT:    or $6, $2, $1
+; MIPS32-NEXT:    addiu	$25, $zero, 0
+; MIPS32-NEXT:    jalr $25
+; MIPS32-NEXT:    srl $4, $3, 16
+; MIPS32-NEXT:    lw $ra, 4($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    addiu $sp, $sp, 8
+Entry:
+  %0 = load <1 x i80>, ptr null, align 16
----------------
yingopq wrote:

Yes, this situation you mentioned also can be solved and the reported bug info was same as null pointer situation. I tested the following test case.

```
$ cat 1.ll
target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
target triple = "mipsel-unknown-linux-unknown"

define void @arg_v1i80(<1 x i80> %vec, ptr %p) {
  store <1 x i80> %vec, ptr %p
  ret void
}

define void @_start(ptr %p) nounwind{
Entry:
  %0 = load <1 x i80>, ptr %p, align 16
  call void @arg_v1i80(<1 x i80> %0)
  ret void
}

```

https://github.com/llvm/llvm-project/pull/109625