[llvm] [AArch64][InstCombine] Bail from combining SRAD on +/-1 divisor (PR #109274)

[Matthew Devereau via llvm-commits]

================
@@ -1972,7 +1972,10 @@ static std::optional<Instruction *> instCombineSVESDIV(InstCombiner &IC,
   ConstantInt *SplatConstantInt = dyn_cast_or_null<ConstantInt>(SplatValue);
   if (!SplatConstantInt)
     return std::nullopt;
+
   APInt Divisor = SplatConstantInt->getValue();
+  if (Divisor.abs().getZExtValue() == 1)
+    return std::nullopt;
----------------
MDevereau wrote:

Yeah that makes sense. I guess the predicate wouldn't matter in that case since it would be a no-op on the whole vector

https://github.com/llvm/llvm-project/pull/109274