[llvm] [AArch64][InstCombine] Bail from combining SRAD on +/-1 divisor (PR #109274)

[Paul Walker via llvm-commits]

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@@ -1972,7 +1972,10 @@ static std::optional<Instruction *> instCombineSVESDIV(InstCombiner &IC,
   ConstantInt *SplatConstantInt = dyn_cast_or_null<ConstantInt>(SplatValue);
   if (!SplatConstantInt)
     return std::nullopt;
+
   APInt Divisor = SplatConstantInt->getValue();
+  if (Divisor.abs().getZExtValue() == 1)
+    return std::nullopt;
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paulwalker-arm wrote:

For the `+1` case, would it be wrong to always return `Vec` here?

https://github.com/llvm/llvm-project/pull/109274