[llvm] [AMDGPU] Do not count implicit VGPRs in SIInsertWaitcnts (PR #109049)

[Stanislav Mekhanoshin via llvm-commits]

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@@ -1752,6 +1752,15 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
         const bool IsVGPR = TRI->isVectorRegister(*MRI, Op.getReg());
         for (int RegNo = Interval.first; RegNo < Interval.second; ++RegNo) {
           if (IsVGPR) {
+            // Implicit VGPR defs and uses are never a part of the memory
+            // instructions description and usually present to account for
+            // super-register liveness. Tied implicit sources on loads though
+            // are real uses.
+            // TODO: Most of the other instructions also have implicit uses
+            // for the liveness accounting only.
+            if (Op.isImplicit() && MI.mayLoadOrStore() && !Op.isTied())
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rampitec wrote:

> I don't see why mayLoadOrStore matters, implicit operands on any instruction shouldn't matter

Implicit operands matter at least with movrel. The check for mayLoadOrStore is really to catch spills which are a real problem. Potentially a very wide loads and stores a problem too.

https://github.com/llvm/llvm-project/pull/109049