[llvm] [AMDGPU] Do not count implicit VGPRs in SIInsertWaitcnts (PR #109049)

[Stanislav Mekhanoshin via llvm-commits]

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@@ -1752,6 +1752,15 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
         const bool IsVGPR = TRI->isVectorRegister(*MRI, Op.getReg());
         for (int RegNo = Interval.first; RegNo < Interval.second; ++RegNo) {
           if (IsVGPR) {
+            // Implicit VGPR defs and uses are never a part of the memory
+            // instructions description and usually present to account for
+            // super-register liveness. Tied implicit sources on loads though
+            // are real uses.
+            // TODO: Most of the other instructions also have implicit uses
+            // for the liveness accounting only.
+            if (Op.isImplicit() && MI.mayLoadOrStore() && !Op.isTied())
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rampitec wrote:

> I'm a bit nervous because lots of instructions are marked mayLoad/mayStore just because they have side effects, not because they are regular load or store instructions.

Do you want a check like isVMEM() || isFLAT() instead?

> I _think_ you can ignore tied uses here because we will still handle the WAW conflict (if any) based on the real def operand that it is tied to.

I've a regression this way in one of the tests with buffer_load and tied def. The wait was lost, hence I've added the check.

https://github.com/llvm/llvm-project/pull/109049