[llvm] [LLVM][TableGen] Change CodeGenSchedule to use const Record pointers (PR #108782)
Rahul Joshi via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 15 16:28:40 PDT 2024
https://github.com/jurahul created https://github.com/llvm/llvm-project/pull/108782
Change CodeGenSchedule to use const Record pointers.
>From dc3d9635da5bca6abb8884a5ea753260aaa9ab3f Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Sun, 15 Sep 2024 10:27:36 -0700
Subject: [PATCH] [LLVM][TableGen] Change CodeGenSchedule to use const Record
pointers
---
.../utils/TableGen/Common/CodeGenSchedule.cpp | 116 +++++++++---------
llvm/utils/TableGen/Common/CodeGenSchedule.h | 35 +++---
llvm/utils/TableGen/DFAPacketizerEmitter.cpp | 17 +--
llvm/utils/TableGen/InstrInfoEmitter.cpp | 3 +-
llvm/utils/TableGen/SubtargetEmitter.cpp | 34 ++---
5 files changed, 107 insertions(+), 98 deletions(-)
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index 33d1da2f848ba9..de2cb67b1f1d53 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -271,8 +271,7 @@ void CodeGenSchedModels::checkSTIPredicates() const {
// Disallow InstructionEquivalenceClasses with an empty instruction list.
for (const Record *R :
Records.getAllDerivedDefinitions("InstructionEquivalenceClass")) {
- RecVec Opcodes = R->getValueAsListOfDefs("Opcodes");
- if (Opcodes.empty()) {
+ if (R->getValueAsListOfDefs("Opcodes").empty()) {
PrintFatalError(R->getLoc(), "Invalid InstructionEquivalenceClass "
"defined with an empty opcode list.");
}
@@ -311,13 +310,13 @@ static void processSTIPredicate(STIPredicateFunction &Fn,
// definitions. Each unique opcode will be associated with an OpcodeInfo
// object.
for (const Record *Def : Fn.getDefinitions()) {
- RecVec Classes = Def->getValueAsListOfDefs("Classes");
+ ConstRecVec Classes = Def->getValueAsListOfConstDefs("Classes");
for (const Record *EC : Classes) {
const Record *Pred = EC->getValueAsDef("Predicate");
if (!Predicate2Index.contains(Pred))
Predicate2Index[Pred] = NumUniquePredicates++;
- RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");
+ ConstRecVec Opcodes = EC->getValueAsListOfConstDefs("Opcodes");
for (const Record *Opcode : Opcodes) {
if (!Opcode2Index.contains(Opcode)) {
Opcode2Index[Opcode] = OpcodeMappings.size();
@@ -342,14 +341,14 @@ static void processSTIPredicate(STIPredicateFunction &Fn,
// Construct a OpcodeInfo object for every unique opcode declared by an
// InstructionEquivalenceClass definition.
for (const Record *Def : Fn.getDefinitions()) {
- RecVec Classes = Def->getValueAsListOfDefs("Classes");
+ ConstRecVec Classes = Def->getValueAsListOfConstDefs("Classes");
const Record *SchedModel = Def->getValueAsDef("SchedModel");
unsigned ProcIndex = ProcModelMap.find(SchedModel)->second;
APInt ProcMask(ProcModelMap.size(), 0);
ProcMask.setBit(ProcIndex);
for (const Record *EC : Classes) {
- RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");
+ ConstRecVec Opcodes = EC->getValueAsListOfConstDefs("Opcodes");
std::vector<int64_t> OpIndices =
EC->getValueAsListOfInts("OperandIndices");
@@ -579,8 +578,7 @@ static void scanSchedRW(const Record *RWDef, ConstRecVec &RWDefs,
// Visit each variant (guarded by a different predicate).
for (const Record *Variant : RWDef->getValueAsListOfDefs("Variants")) {
// Visit each RW in the sequence selected by the current variant.
- RecVec Selected = Variant->getValueAsListOfDefs("Selected");
- for (Record *SelDef : Selected)
+ for (const Record *SelDef : Variant->getValueAsListOfDefs("Selected"))
scanSchedRW(SelDef, RWDefs, RWSet);
}
}
@@ -601,8 +599,7 @@ void CodeGenSchedModels::collectSchedRW() {
const Record *SchedDef = Inst->TheDef;
if (SchedDef->isValueUnset("SchedRW"))
continue;
- RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
- for (Record *RW : RWs) {
+ for (const Record *RW : SchedDef->getValueAsListOfDefs("SchedRW")) {
if (RW->isSubClassOf("SchedWrite"))
scanSchedRW(RW, SWDefs, RWSet);
else {
@@ -614,8 +611,8 @@ void CodeGenSchedModels::collectSchedRW() {
// Find all ReadWrites referenced by InstRW.
for (const Record *InstRWDef : Records.getAllDerivedDefinitions("InstRW")) {
// For all OperandReadWrites.
- RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites");
- for (Record *RWDef : RWDefs) {
+ for (const Record *RWDef :
+ InstRWDef->getValueAsListOfDefs("OperandReadWrites")) {
if (RWDef->isSubClassOf("SchedWrite"))
scanSchedRW(RWDef, SWDefs, RWSet);
else {
@@ -627,8 +624,8 @@ void CodeGenSchedModels::collectSchedRW() {
// Find all ReadWrites referenced by ItinRW.
for (const Record *ItinRWDef : Records.getAllDerivedDefinitions("ItinRW")) {
// For all OperandReadWrites.
- RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites");
- for (Record *RWDef : RWDefs) {
+ for (const Record *RWDef :
+ ItinRWDef->getValueAsListOfDefs("OperandReadWrites")) {
if (RWDef->isSubClassOf("SchedWrite"))
scanSchedRW(RWDef, SWDefs, RWSet);
else {
@@ -672,7 +669,7 @@ void CodeGenSchedModels::collectSchedRW() {
for (CodeGenSchedRW &CGRW : SchedWrites) {
if (!CGRW.IsSequence)
continue;
- findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence,
+ findRWs(CGRW.TheDef->getValueAsListOfConstDefs("Writes"), CGRW.Sequence,
/*IsRead=*/false);
}
// Initialize Aliases vectors.
@@ -726,9 +723,10 @@ unsigned CodeGenSchedModels::getSchedRWIdx(const Record *Def,
return I == RWVec.end() ? 0 : std::distance(RWVec.begin(), I);
}
-static void splitSchedReadWrites(const RecVec &RWDefs, RecVec &WriteDefs,
- RecVec &ReadDefs) {
- for (Record *RWDef : RWDefs) {
+static void splitSchedReadWrites(const ConstRecVec &RWDefs,
+ ConstRecVec &WriteDefs,
+ ConstRecVec &ReadDefs) {
+ for (const Record *RWDef : RWDefs) {
if (RWDef->isSubClassOf("SchedWrite"))
WriteDefs.push_back(RWDef);
else {
@@ -739,19 +737,19 @@ static void splitSchedReadWrites(const RecVec &RWDefs, RecVec &WriteDefs,
}
// Split the SchedReadWrites defs and call findRWs for each list.
-void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &Writes,
+void CodeGenSchedModels::findRWs(const ConstRecVec &RWDefs, IdxVec &Writes,
IdxVec &Reads) const {
- RecVec WriteDefs;
- RecVec ReadDefs;
+ ConstRecVec WriteDefs;
+ ConstRecVec ReadDefs;
splitSchedReadWrites(RWDefs, WriteDefs, ReadDefs);
findRWs(WriteDefs, Writes, false);
findRWs(ReadDefs, Reads, true);
}
// Call getSchedRWIdx for all elements in a sequence of SchedRW defs.
-void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,
+void CodeGenSchedModels::findRWs(const ConstRecVec &RWDefs, IdxVec &RWs,
bool IsRead) const {
- for (Record *RWDef : RWDefs) {
+ for (const Record *RWDef : RWDefs) {
unsigned Idx = getSchedRWIdx(RWDef, IsRead);
assert(Idx && "failed to collect SchedReadWrite");
RWs.push_back(Idx);
@@ -859,7 +857,8 @@ void CodeGenSchedModels::collectSchedClasses() {
Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary");
IdxVec Writes, Reads;
if (!Inst->TheDef->isValueUnset("SchedRW"))
- findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
+ findRWs(Inst->TheDef->getValueAsListOfConstDefs("SchedRW"), Writes,
+ Reads);
// ProcIdx == 0 indicates the class applies to all processors.
unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/ {0});
@@ -921,7 +920,8 @@ void CodeGenSchedModels::collectSchedClasses() {
<< InstName);
IdxVec Writes;
IdxVec Reads;
- findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
+ findRWs(RWDef->getValueAsListOfConstDefs("OperandReadWrites"), Writes,
+ Reads);
LLVM_DEBUG({
for (unsigned WIdx : Writes)
dbgs() << " " << SchedWrites[WIdx].Name;
@@ -950,10 +950,9 @@ CodeGenSchedModels::getSchedClassIdx(const CodeGenInstruction &Inst) const {
}
std::string
-CodeGenSchedModels::createSchedClassName(Record *ItinClassDef,
+CodeGenSchedModels::createSchedClassName(const Record *ItinClassDef,
ArrayRef<unsigned> OperWrites,
ArrayRef<unsigned> OperReads) {
-
std::string Name;
if (ItinClassDef && ItinClassDef->getName() != "NoItinerary")
Name = std::string(ItinClassDef->getName());
@@ -983,7 +982,7 @@ CodeGenSchedModels::createSchedClassName(const ConstRecVec &InstDefs) {
/// Add an inferred sched class from an itinerary class and per-operand list of
/// SchedWrites and SchedReads. ProcIndices contains the set of IDs of
/// processors that may utilize this class.
-unsigned CodeGenSchedModels::addSchedClass(Record *ItinClassDef,
+unsigned CodeGenSchedModels::addSchedClass(const Record *ItinClassDef,
ArrayRef<unsigned> OperWrites,
ArrayRef<unsigned> OperReads,
ArrayRef<unsigned> ProcIndices) {
@@ -1131,7 +1130,8 @@ void CodeGenSchedModels::collectProcItins() {
if (!ProcModel.hasItineraries())
continue;
- RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");
+ ConstRecVec ItinRecords =
+ ProcModel.ItinsDef->getValueAsListOfConstDefs("IID");
assert(!ItinRecords.empty() && "ProcModel.hasItineraries is incorrect");
// Populate ItinDefList with Itinerary records.
@@ -1139,7 +1139,7 @@ void CodeGenSchedModels::collectProcItins() {
// Insert each itinerary data record in the correct position within
// the processor model's ItinDefList.
- for (Record *ItinData : ItinRecords) {
+ for (const Record *ItinData : ItinRecords) {
const Record *ItinDef = ItinData->getValueAsDef("TheClass");
bool FoundClass = false;
@@ -1217,14 +1217,15 @@ void CodeGenSchedModels::inferSchedClasses() {
}
/// Infer classes from per-processor itinerary resources.
-void CodeGenSchedModels::inferFromItinClass(Record *ItinClassDef,
+void CodeGenSchedModels::inferFromItinClass(const Record *ItinClassDef,
unsigned FromClassIdx) {
for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
const CodeGenProcModel &PM = ProcModels[PIdx];
// For all ItinRW entries.
bool HasMatch = false;
for (const Record *Rec : PM.ItinRWDefs) {
- RecVec Matched = Rec->getValueAsListOfDefs("MatchedItinClasses");
+ ConstRecVec Matched =
+ Rec->getValueAsListOfConstDefs("MatchedItinClasses");
if (!llvm::is_contained(Matched, ItinClassDef))
continue;
if (HasMatch)
@@ -1233,7 +1234,8 @@ void CodeGenSchedModels::inferFromItinClass(Record *ItinClassDef,
" in ItinResources for " + PM.ModelName);
HasMatch = true;
IdxVec Writes, Reads;
- findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
+ findRWs(Rec->getValueAsListOfConstDefs("OperandReadWrites"), Writes,
+ Reads);
inferFromRW(Writes, Reads, FromClassIdx, PIdx);
}
}
@@ -1255,7 +1257,7 @@ void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) {
if (II == IE)
continue;
IdxVec Writes, Reads;
- findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
+ findRWs(Rec->getValueAsListOfConstDefs("OperandReadWrites"), Writes, Reads);
unsigned PIdx = getProcModel(Rec->getValueAsDef("SchedModel")).Index;
inferFromRW(Writes, Reads, SCIdx, PIdx); // May mutate SchedClasses.
SchedClasses[SCIdx].InstRWProcIndices.insert(PIdx);
@@ -1348,7 +1350,8 @@ bool PredTransitions::mutuallyExclusive(Record *PredDef,
const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(PC.RWIdx, PC.IsRead);
assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant");
- RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");
+ ConstRecVec Variants =
+ SchedRW.TheDef->getValueAsListOfConstDefs("Variants");
if (any_of(Variants, [PredDef](const Record *R) {
return R->getValueAsDef("Predicate") == PredDef;
})) {
@@ -1414,8 +1417,8 @@ void PredTransitions::getIntersectingVariants(
}
if (VarProcIdx == 0 || VarProcIdx == TransVec[TransIdx].ProcIndex) {
// Push each variant. Assign TransVecIdx later.
- const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
- for (Record *VarDef : VarDefs)
+ for (const Record *VarDef :
+ SchedRW.TheDef->getValueAsListOfDefs("Variants"))
Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0);
if (VarProcIdx == 0)
GenericRW = true;
@@ -1446,8 +1449,7 @@ void PredTransitions::getIntersectingVariants(
SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
if (AliasRW.HasVariants) {
- const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");
- for (Record *VD : VarDefs)
+ for (const Record *VD : AliasRW.TheDef->getValueAsListOfDefs("Variants"))
Variants.emplace_back(VD, AliasRW.Index, AliasProcIdx, 0);
}
if (AliasRW.IsSequence)
@@ -1495,7 +1497,8 @@ void PredTransitions::pushVariant(const TransVariant &VInfo, bool IsRead) {
if (VInfo.VarOrSeqDef->isSubClassOf("SchedVar")) {
Record *PredDef = VInfo.VarOrSeqDef->getValueAsDef("Predicate");
Trans.PredTerm.emplace_back(IsRead, VInfo.RWIdx, PredDef);
- RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");
+ ConstRecVec SelectedDefs =
+ VInfo.VarOrSeqDef->getValueAsListOfConstDefs("Selected");
SchedModels.findRWs(SelectedDefs, SelectedRWs, IsRead);
} else {
assert(VInfo.VarOrSeqDef->isSubClassOf("WriteSequence") &&
@@ -1761,12 +1764,14 @@ void CodeGenSchedModels::inferFromRW(ArrayRef<unsigned> OperWrites,
// Check if any processor resource group contains all resource records in
// SubUnits.
-bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) {
+bool CodeGenSchedModels::hasSuperGroup(ConstRecVec &SubUnits,
+ CodeGenProcModel &PM) {
for (const Record *ProcResourceDef : PM.ProcResourceDefs) {
if (!ProcResourceDef->isSubClassOf("ProcResGroup"))
continue;
- RecVec SuperUnits = ProcResourceDef->getValueAsListOfDefs("Resources");
- RecIter RI = SubUnits.begin(), RE = SubUnits.end();
+ ConstRecVec SuperUnits =
+ ProcResourceDef->getValueAsListOfConstDefs("Resources");
+ auto RI = SubUnits.begin(), RE = SubUnits.end();
for (; RI != RE; ++RI) {
if (!is_contained(SuperUnits, *RI)) {
break;
@@ -1783,13 +1788,13 @@ void CodeGenSchedModels::verifyProcResourceGroups(CodeGenProcModel &PM) {
for (unsigned i = 0, e = PM.ProcResourceDefs.size(); i < e; ++i) {
if (!PM.ProcResourceDefs[i]->isSubClassOf("ProcResGroup"))
continue;
- RecVec CheckUnits =
- PM.ProcResourceDefs[i]->getValueAsListOfDefs("Resources");
+ ConstRecVec CheckUnits =
+ PM.ProcResourceDefs[i]->getValueAsListOfConstDefs("Resources");
for (unsigned j = i + 1; j < e; ++j) {
if (!PM.ProcResourceDefs[j]->isSubClassOf("ProcResGroup"))
continue;
- RecVec OtherUnits =
- PM.ProcResourceDefs[j]->getValueAsListOfDefs("Resources");
+ ConstRecVec OtherUnits =
+ PM.ProcResourceDefs[j]->getValueAsListOfConstDefs("Resources");
if (std::find_first_of(CheckUnits.begin(), CheckUnits.end(),
OtherUnits.begin(),
OtherUnits.end()) != CheckUnits.end()) {
@@ -1828,7 +1833,7 @@ void CodeGenSchedModels::collectRegisterFiles() {
"Invalid RegisterFile with zero physical registers");
}
- RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");
+ ConstRecVec RegisterClasses = RF->getValueAsListOfConstDefs("RegClasses");
std::vector<int64_t> RegisterCosts = RF->getValueAsListOfInts("RegCosts");
ListInit *MoveElimInfo = RF->getValueAsListInit("AllowMoveElimination");
for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) {
@@ -1866,7 +1871,8 @@ void CodeGenSchedModels::collectProcResources() {
Record *RWModelDef = RW->getValueAsDef("SchedModel");
unsigned PIdx = getProcModel(RWModelDef).Index;
IdxVec Writes, Reads;
- findRWs(RW->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
+ findRWs(RW->getValueAsListOfConstDefs("OperandReadWrites"), Writes,
+ Reads);
collectRWResources(Writes, Reads, PIdx);
}
@@ -2004,13 +2010,13 @@ void CodeGenSchedModels::checkCompleteness() {
}
// Collect itinerary class resources for each processor.
-void CodeGenSchedModels::collectItinProcResources(Record *ItinClassDef) {
+void CodeGenSchedModels::collectItinProcResources(const Record *ItinClassDef) {
for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
const CodeGenProcModel &PM = ProcModels[PIdx];
// For all ItinRW entries.
bool HasMatch = false;
for (const Record *R : PM.ItinRWDefs) {
- RecVec Matched = R->getValueAsListOfDefs("MatchedItinClasses");
+ ConstRecVec Matched = R->getValueAsListOfConstDefs("MatchedItinClasses");
if (!llvm::is_contained(Matched, ItinClassDef))
continue;
if (HasMatch)
@@ -2019,7 +2025,7 @@ void CodeGenSchedModels::collectItinProcResources(Record *ItinClassDef) {
" in ItinResources for " + PM.ModelName);
HasMatch = true;
IdxVec Writes, Reads;
- findRWs(R->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
+ findRWs(R->getValueAsListOfConstDefs("OperandReadWrites"), Writes, Reads);
collectRWResources(Writes, Reads, PIdx);
}
}
@@ -2139,8 +2145,8 @@ void CodeGenSchedModels::addWriteRes(const Record *ProcWriteResDef,
WRDefs.push_back(ProcWriteResDef);
// Visit ProcResourceKinds referenced by the newly discovered WriteRes.
- RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");
- for (const Record *ProcResDef : ProcResDefs) {
+ for (const Record *ProcResDef :
+ ProcWriteResDef->getValueAsListOfDefs("ProcResources")) {
addProcResource(ProcResDef, ProcModels[PIdx], ProcWriteResDef->getLoc());
}
}
@@ -2186,7 +2192,7 @@ bool CodeGenProcModel::isUnsupported(const CodeGenInstruction &Inst) const {
bool CodeGenProcModel::hasReadOfWrite(const Record *WriteDef) const {
for (auto &RADef : ReadAdvanceDefs) {
- RecVec ValidWrites = RADef->getValueAsListOfDefs("ValidWrites");
+ ConstRecVec ValidWrites = RADef->getValueAsListOfConstDefs("ValidWrites");
if (is_contained(ValidWrites, WriteDef))
return true;
}
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.h b/llvm/utils/TableGen/Common/CodeGenSchedule.h
index ff85ac3968593b..f43c856b274ce8 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.h
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.h
@@ -33,8 +33,6 @@ class CodeGenTarget;
class CodeGenSchedModels;
class CodeGenInstruction;
-using RecVec = std::vector<Record *>;
-using RecIter = RecVec::const_iterator;
using ConstRecVec = std::vector<const Record *>;
using ConstRecIter = ConstRecVec::const_iterator;
@@ -132,7 +130,7 @@ struct CodeGenSchedTransition {
struct CodeGenSchedClass {
unsigned Index;
std::string Name;
- Record *ItinClassDef;
+ const Record *ItinClassDef;
IdxVec Writes;
IdxVec Reads;
@@ -149,10 +147,11 @@ struct CodeGenSchedClass {
// InstRWs processor indices. Filled in inferFromInstRWs
DenseSet<unsigned> InstRWProcIndices;
- CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef)
+ CodeGenSchedClass(unsigned Index, std::string Name,
+ const Record *ItinClassDef)
: Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
- bool isKeyEqual(Record *IC, ArrayRef<unsigned> W,
+ bool isKeyEqual(const Record *IC, ArrayRef<unsigned> W,
ArrayRef<unsigned> R) const {
return ItinClassDef == IC && ArrayRef(Writes) == W && ArrayRef(Reads) == R;
}
@@ -172,10 +171,10 @@ struct CodeGenSchedClass {
/// registers used by the register renamer. Register costs are defined at
/// register class granularity.
struct CodeGenRegisterCost {
- Record *RCDef;
+ const Record *RCDef;
unsigned Cost;
bool AllowMoveElimination;
- CodeGenRegisterCost(Record *RC, unsigned RegisterCost,
+ CodeGenRegisterCost(const Record *RC, unsigned RegisterCost,
bool AllowMoveElim = false)
: RCDef(RC), Cost(RegisterCost), AllowMoveElimination(AllowMoveElim) {}
CodeGenRegisterCost(const CodeGenRegisterCost &) = default;
@@ -231,7 +230,7 @@ struct CodeGenProcModel {
// Array of InstrItinData records indexed by a CodeGenSchedClass index.
// This list is empty if the Processor has no value for Itineraries.
// Initialized by collectProcItins().
- RecVec ItinDefList;
+ ConstRecVec ItinDefList;
// Map itinerary classes to per-operand resources.
// This list is empty if no ItinRW refers to this Processor.
@@ -239,7 +238,7 @@ struct CodeGenProcModel {
// List of unsupported feature.
// This list is empty if the Processor has no UnsupportedFeatures.
- RecVec UnsupportedFeaturesDefs;
+ ConstRecVec UnsupportedFeaturesDefs;
// All read/write resources associated with this processor.
ConstRecVec WriteResDefs;
@@ -530,13 +529,13 @@ class CodeGenSchedModels {
const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
}
- CodeGenSchedRW &getSchedRW(Record *Def) {
+ CodeGenSchedRW &getSchedRW(const Record *Def) {
bool IsRead = Def->isSubClassOf("SchedRead");
unsigned Idx = getSchedRWIdx(Def, IsRead);
return const_cast<CodeGenSchedRW &>(IsRead ? getSchedRead(Idx)
: getSchedWrite(Idx));
}
- const CodeGenSchedRW &getSchedRW(Record *Def) const {
+ const CodeGenSchedRW &getSchedRW(const Record *Def) const {
return const_cast<CodeGenSchedModels &>(*this).getSchedRW(Def);
}
@@ -564,13 +563,13 @@ class CodeGenSchedModels {
unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
- void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
- void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
+ void findRWs(const ConstRecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
+ void findRWs(const ConstRecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
const CodeGenProcModel &ProcModel) const;
- unsigned addSchedClass(Record *ItinDef, ArrayRef<unsigned> OperWrites,
+ unsigned addSchedClass(const Record *ItinDef, ArrayRef<unsigned> OperWrites,
ArrayRef<unsigned> OperReads,
ArrayRef<unsigned> ProcIndices);
@@ -603,7 +602,7 @@ class CodeGenSchedModels {
void collectOptionalProcessorInfo();
- std::string createSchedClassName(Record *ItinClassDef,
+ std::string createSchedClassName(const Record *ItinClassDef,
ArrayRef<unsigned> OperWrites,
ArrayRef<unsigned> OperReads);
std::string createSchedClassName(const ConstRecVec &InstDefs);
@@ -629,15 +628,15 @@ class CodeGenSchedModels {
void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads,
unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices);
- void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
+ void inferFromItinClass(const Record *ItinClassDef, unsigned FromClassIdx);
void inferFromInstRWs(unsigned SCIdx);
- bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM);
+ bool hasSuperGroup(ConstRecVec &SubUnits, CodeGenProcModel &PM);
void verifyProcResourceGroups(CodeGenProcModel &PM);
void collectProcResources();
- void collectItinProcResources(Record *ItinClassDef);
+ void collectItinProcResources(const Record *ItinClassDef);
void collectRWResources(unsigned RWIdx, bool IsRead,
ArrayRef<unsigned> ProcIndices);
diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
index 55cb39c9de5faa..4070bafded9cc2 100644
--- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -78,8 +78,9 @@ class DFAPacketizerEmitter {
// functional units.
int collectAllComboFuncs(ArrayRef<Record *> ComboFuncList);
- ResourceVector getResourcesForItinerary(Record *Itinerary);
- void createScheduleClasses(unsigned ItineraryIdx, const RecVec &Itineraries);
+ ResourceVector getResourcesForItinerary(const Record *Itinerary);
+ void createScheduleClasses(unsigned ItineraryIdx,
+ const ConstRecVec &Itineraries);
// Emit code for a subset of itineraries.
void emitForItineraries(raw_ostream &OS,
@@ -174,12 +175,12 @@ int DFAPacketizerEmitter::collectAllComboFuncs(
}
ResourceVector
-DFAPacketizerEmitter::getResourcesForItinerary(Record *Itinerary) {
+DFAPacketizerEmitter::getResourcesForItinerary(const Record *Itinerary) {
ResourceVector Resources;
assert(Itinerary);
- for (Record *StageDef : Itinerary->getValueAsListOfDefs("Stages")) {
+ for (const Record *StageDef : Itinerary->getValueAsListOfDefs("Stages")) {
uint64_t StageResources = 0;
- for (Record *Unit : StageDef->getValueAsListOfDefs("Units")) {
+ for (const Record *Unit : StageDef->getValueAsListOfDefs("Units")) {
StageResources |= FUNameToBitsMap[std::string(Unit->getName())];
}
if (StageResources != 0)
@@ -188,10 +189,10 @@ DFAPacketizerEmitter::getResourcesForItinerary(Record *Itinerary) {
return Resources;
}
-void DFAPacketizerEmitter::createScheduleClasses(unsigned ItineraryIdx,
- const RecVec &Itineraries) {
+void DFAPacketizerEmitter::createScheduleClasses(
+ unsigned ItineraryIdx, const ConstRecVec &Itineraries) {
unsigned Idx = 0;
- for (Record *Itinerary : Itineraries) {
+ for (const Record *Itinerary : Itineraries) {
if (!Itinerary) {
ScheduleClasses.push_back({ItineraryIdx, Idx++, 0, ResourceVector{}});
continue;
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 4e2138d15fde50..5830cdae709629 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -672,7 +672,8 @@ void InstrInfoEmitter::emitLogicalOperandTypeMappings(
void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
StringRef TargetName) {
- RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
+ ArrayRef<const Record *> TIIPredicates =
+ Records.getAllDerivedDefinitions("TIIPredicate");
OS << "#ifdef GET_INSTRINFO_MC_HELPER_DECLS\n";
OS << "#undef GET_INSTRINFO_MC_HELPER_DECLS\n\n";
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 394e2eb42c15d2..c568f6747f4f9a 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -284,7 +284,7 @@ unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS,
<< "\"" << CommandLineName << "\", "
<< "\"" << Desc << "\", " << Target << "::" << Name << ", ";
- RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies");
+ ConstRecVec ImpliesList = Feature->getValueAsListOfConstDefs("Implies");
printFeatureMask(OS, ImpliesList, FeatureMap);
@@ -320,8 +320,9 @@ unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS,
for (const Record *Processor : ProcessorList) {
StringRef Name = Processor->getValueAsString("Name");
- RecVec FeatureList = Processor->getValueAsListOfDefs("Features");
- RecVec TuneFeatureList = Processor->getValueAsListOfDefs("TuneFeatures");
+ ConstRecVec FeatureList = Processor->getValueAsListOfConstDefs("Features");
+ ConstRecVec TuneFeatureList =
+ Processor->getValueAsListOfConstDefs("TuneFeatures");
// Emit as "{ "cpu", "description", 0, { f1 , f2 , ... fn } },".
OS << " { "
@@ -366,7 +367,7 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
ItinString += " { " + itostr(Cycles) + ", ";
// Get unit list
- RecVec UnitList = Stage->getValueAsListOfDefs("Units");
+ ConstRecVec UnitList = Stage->getValueAsListOfConstDefs("Units");
// For each unit
for (unsigned j = 0, M = UnitList.size(); j < M;) {
@@ -444,7 +445,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(
if (!ItinsDefSet.insert(ProcModel.ItinsDef).second)
continue;
- RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");
+ ConstRecVec FUs = ProcModel.ItinsDef->getValueAsListOfConstDefs("FU");
if (FUs.empty())
continue;
@@ -458,7 +459,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(
OS << "} // end namespace " << Name << "FU\n";
- RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
+ ConstRecVec BPs = ProcModel.ItinsDef->getValueAsListOfConstDefs("BP");
if (!BPs.empty()) {
OS << "\n// Pipeline forwarding paths for itineraries \"" << Name
<< "\"\n"
@@ -682,8 +683,7 @@ void SubtargetEmitter::EmitProcessorResourceSubUnits(
const Record *PRDef = ProcModel.ProcResourceDefs[i];
if (!PRDef->isSubClassOf("ProcResGroup"))
continue;
- RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
- for (const Record *RUDef : ResUnits) {
+ for (const Record *RUDef : PRDef->getValueAsListOfDefs("Resources")) {
const Record *RU =
SchedModels.findProcResUnits(RUDef, ProcModel, PRDef->getLoc());
for (unsigned J = 0; J < RU->getValueAsInt("NumUnits"); ++J) {
@@ -842,8 +842,7 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
const unsigned SubUnitsBeginOffset = SubUnitsOffset;
int BufferSize = PRDef->getValueAsInt("BufferSize");
if (PRDef->isSubClassOf("ProcResGroup")) {
- RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
- for (const Record *RU : ResUnits) {
+ for (const Record *RU : PRDef->getValueAsListOfDefs("Resources")) {
NumUnits += RU->getValueAsInt("NumUnits");
SubUnitsOffset += RU->getValueAsInt("NumUnits");
}
@@ -1028,7 +1027,7 @@ void SubtargetEmitter::ExpandProcResources(
for (const Record *PR : PM.ProcResourceDefs) {
if (PR == PRDef || !PR->isSubClassOf("ProcResGroup"))
continue;
- RecVec SuperResources = PR->getValueAsListOfDefs("Resources");
+ ConstRecVec SuperResources = PR->getValueAsListOfConstDefs("Resources");
ConstRecIter SubI = SubResources.begin(), SubE = SubResources.end();
for (; SubI != SubE; ++SubI) {
if (!is_contained(SuperResources, *SubI)) {
@@ -1105,16 +1104,18 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
if (RWDef) {
Writes.clear();
Reads.clear();
- SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
- Writes, Reads);
+ SchedModels.findRWs(
+ RWDef->getValueAsListOfConstDefs("OperandReadWrites"), Writes,
+ Reads);
}
}
if (Writes.empty()) {
// Check this processor's itinerary class resources.
for (const Record *I : ProcModel.ItinRWDefs) {
- RecVec Matched = I->getValueAsListOfDefs("MatchedItinClasses");
+ ConstRecVec Matched =
+ I->getValueAsListOfConstDefs("MatchedItinClasses");
if (is_contained(Matched, SC.ItinClassDef)) {
- SchedModels.findRWs(I->getValueAsListOfDefs("OperandReadWrites"),
+ SchedModels.findRWs(I->getValueAsListOfConstDefs("OperandReadWrites"),
Writes, Reads);
break;
}
@@ -1274,7 +1275,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
break;
}
- RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites");
+ ConstRecVec ValidWrites =
+ ReadAdvance->getValueAsListOfConstDefs("ValidWrites");
IdxVec WriteIDs;
if (ValidWrites.empty())
WriteIDs.push_back(0);
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