[llvm] [X86] Fix missing check of rotate <-> shift equivilence (Issue 108722) (PR #108767)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

Author: None (goldsteinn)

<details>
<summary>Changes</summary>

- **[X86] Add test for issue 108722; NFC**
- **[X86] Fix missing check of rotate <-> shift equivilence (Issue 108722)**

Previous code was checking that rotate and shift where equivilent when
transforming shift -> rotate but not the other way around.


---
Full diff: https://github.com/llvm/llvm-project/pull/108767.diff


2 Files Affected:

- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+1-1) 
- (modified) llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll (+24) 


``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 053b2354f6aeb6..d73c49124315a9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3489,7 +3489,7 @@ unsigned X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(
 
   // We prefer rotate for vectors of if we won't get a zext mask with SRL
   // (PreferRotate will be set in the latter case).
-  if (PreferRotate || VT.isVector())
+  if (PreferRotate || !MayTransformRotate || VT.isVector())
     return ShiftOpc;
 
   // Non-vector type and we have a zext mask with SRL.
diff --git a/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll b/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
index 67070b989786db..227de9ad0ab690 100644
--- a/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
+++ b/llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
@@ -994,6 +994,30 @@ define i1 @shr_to_rotate_eq_i32_s5(i32 %x) {
   ret i1 %r
 }
 
+define i32 @issue108722(i32 %0) {
+; CHECK-NOBMI-LABEL: issue108722:
+; CHECK-NOBMI:       # %bb.0:
+; CHECK-NOBMI-NEXT:    movl %edi, %ecx
+; CHECK-NOBMI-NEXT:    roll $24, %ecx
+; CHECK-NOBMI-NEXT:    xorl %eax, %eax
+; CHECK-NOBMI-NEXT:    cmpl %edi, %ecx
+; CHECK-NOBMI-NEXT:    sete %al
+; CHECK-NOBMI-NEXT:    retq
+;
+; CHECK-BMI2-LABEL: issue108722:
+; CHECK-BMI2:       # %bb.0:
+; CHECK-BMI2-NEXT:    rorxl $8, %edi, %ecx
+; CHECK-BMI2-NEXT:    xorl %eax, %eax
+; CHECK-BMI2-NEXT:    cmpl %edi, %ecx
+; CHECK-BMI2-NEXT:    sete %al
+; CHECK-BMI2-NEXT:    retq
+  %2 = tail call i32 @llvm.fshl.i32(i32 %0, i32 %0, i32 24)
+  %3 = icmp eq i32 %2, %0
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; CHECK-AVX: {{.*}}
 ; CHECK-NOBMI-SSE2: {{.*}}

``````````

</details>


https://github.com/llvm/llvm-project/pull/108767